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1.发明授权Structure for monitoring stress induced failures in interlevel dielectric layers of solder bump integrated circuits 有权用于监测焊料凸块集成电路的层间电介质层中的应力诱发故障的结构公开(公告)号：US08653662B2
公开(公告)日：2014-02-18
申请号：US13461912
申请日：2012-05-02
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/053 , H01L23/12
CPC分类号： H01L22/34 , H01L23/49816 , H01L23/50 , H01L23/5283 , H01L23/5329 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05008 , H01L2224/05073 , H01L2224/05124 , H01L2224/0554 , H01L2224/05572 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/14515 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/15311 , H01L2924/00 , H01L2924/014 , H01L2224/05552
摘要： A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density.
摘要翻译： 一种用于监测层间介电应力损伤的结构和方法。 该结构包括一个监测焊锡凸块和一般焊锡凸块; 在衬底和监测焊料凸点之间的一组层叠的层间电介质层和正常的焊料凸点，一个或多个包含介电常数为2.4或更小的超低K材料的超低K电介质层; 在超低K电介质层中的监视器焊料凸块正下方的区域中的监视器结构，并且其中在监视器焊料凸块正下方的区域中的至少一个超低K电介质层中的导体密度小于规定的最小值 正常焊锡凸块下的超低K电介质层的相应区域的密度和导体密度大于规定的最小密度。
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公开(公告)号：US08759977B2
公开(公告)日：2014-06-24
申请号：US13459785
申请日：2012-04-30
CPC分类号： H01L21/768 , H01L23/5226 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.
摘要翻译： 集成电路结构包括形成层压结构的多个绝缘体层（彼此连接）。 进一步包括在每个绝缘体层内的开口，以及通孔开口内的导电通孔材料。 相邻绝缘体层的对应的通孔内的导电通孔材料电连接以形成通过层压结构的顶表面和底表面之间的绝缘体层的连续的电通路。 在每个连续的电通路中，通孔相对于彼此定位，以形成通过层压结构的导电过孔材料的对角线结构路径。 相邻绝缘体层的相应通孔开始部分重叠。 对角结构路径与顶面和底面非垂直。
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3.发明授权Semiconductor test chip device to mimic field thermal mini-cycles to assess reliability 有权半导体测试芯片器件模拟现场热敏小周期来评估可靠性公开(公告)号：US08586982B2
公开(公告)日：2013-11-19
申请号：US12862844
申请日：2010-08-25
CPC分类号： G01R31/2856 , G01R31/2875
摘要： A semiconductor test device including a plurality of conductive layers, each of the layers comprising integrated circuit devices, a plurality of insulating layers between the conductive layers, a plurality of heat generating structures positioned between the insulating layers and the conductive layers, each of the heat generating structures being sized and positioned to only heat a predetermined limited area of the plurality of layers, a plurality of thermal monitors positioned within each of the plurality of layers, a control unit operatively connected to the heat generating structures and the thermal monitors, the control unit individually cycling the heat generating structures on and off for multiple heat cycles, such that different areas of the layers are treated to different heat cycles.
摘要翻译： 一种半导体测试装置，包括多个导电层，每个层包括集成电路器件，导电层之间的多个绝缘层，位于绝缘层和导电层之间的多个发热结构，每个热量 产生的结构的大小和位置仅仅加热多个层中的预定限制区域，多个位于多个层中的每一个层内的热监测器，可操作地连接到发热结构和热监测器的控制单元， 单元单独地将发热结构打开和关闭多个热循环，使得不同的层的区域被处理到不同的热循环。
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4.发明申请CIRCUIT FOR DETECTING STRUCTURAL DEFECTS IN AN INTEGRATED CIRCUIT CHIP, METHODS OF USE AND MANUFACTURE AND DESIGN STRUCTURES 有权用于检测集成电路芯片中的结构缺陷的电路，使用和制造方法和设计结构公开(公告)号：US20120187953A1
公开(公告)日：2012-07-26
申请号：US13010057
申请日：2011-01-20
申请人： Luke D. LACROIX , Mark C.H. Lamorey , Steven F. Oakland , Janak G. Patel , Kerry P. Pfarr , Peter Slota, JR. , David B. Stone
发明人： Luke D. LACROIX , Mark C.H. Lamorey , Steven F. Oakland , Janak G. Patel , Kerry P. Pfarr , Peter Slota, JR. , David B. Stone
IPC分类号： G01R31/02
CPC分类号： G01R31/2884 , G01R31/2896 , H01L21/76895 , H01L22/32
摘要： Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.
摘要翻译： 本文提供了检测电路，使用和制造方法以及设计结构。 该结构包括穿过集成电路的一个或多个金属层的至少一个信号线。 电路耦合到所述至少一个信号线，其被构造为接收具有来自至少一个信号线的已知信号或来自不同电位的信号的信号，并且基于哪个信号被接收，确定是否存在 集成电路中的结构缺陷。
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5.发明申请SEMICONDUCTOR TEST CHIP DEVICE TO MIMIC FIELD THERMAL MINI-CYCLES TO ASSESS RELIABILITY 有权半导体测试芯片设备到MIMIC领域的热循环以评估可靠性公开(公告)号：US20120049874A1
公开(公告)日：2012-03-01
申请号：US12862844
申请日：2010-08-25
IPC分类号： G01R31/26
CPC分类号： G01R31/2856 , G01R31/2875
摘要： A semiconductor test device including a plurality of conductive layers, each of the layers comprising integrated circuit devices, a plurality of insulating layers between the conductive layers, a plurality of heat generating structures positioned between the insulating layers and the conductive layers, each of the heat generating structures being sized and positioned to only heat a predetermined limited area of the plurality of layers, a plurality of thermal monitors positioned within each of the plurality of layers, a control unit operatively connected to the heat generating structures and the thermal monitors, the control unit individually cycling the heat generating structures on and off for multiple heat cycles, such that different areas of the layers are treated to different heat cycles.
摘要翻译： 一种半导体测试装置，包括多个导电层，每个层包括集成电路器件，导电层之间的多个绝缘层，位于绝缘层和导电层之间的多个发热结构，每个热量 产生的结构的大小和位置仅仅加热多个层中的预定限制区域，多个位于多个层中的每一个层内的热监测器，可操作地连接到发热结构和热监测器的控制单元， 单元单独地将发热结构打开和关闭多个热循环，使得不同的层的区域被处理到不同的热循环。
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公开(公告)号：US09093445B2
公开(公告)日：2015-07-28
申请号：US13219084
申请日：2011-08-26
IPC分类号： H03K3/00 , H01L23/50 , H01L25/065 , G11C11/4072
CPC分类号： H01L23/50 , G11C11/4072 , H01L25/0657 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2924/0002 , H03K3/00 , H01L2924/00
摘要： Methods and structures are provided for packaging identically processed chips in a stacked structure. A latch chain includes a first latch chain, having a single or multiple latches, associated with a first chip. The first latch chain is structured to read data information from the first chip. The latch chain includes a second latch chain, having a single or multiple latches, associated with a second chip. The second latch chain is structured to read data information from the second chip. The first latch chain and the second latch chain are connected to one another such that form a single latch chain that crosses chip boundaries. The first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.
摘要翻译： 提供了用于在堆叠结构中包装相同处理的芯片的方法和结构。 闩锁链包括与第一芯片相关联的具有单个或多个闩锁的第一闩锁链。 第一锁存链被构造成从第一芯片读取数据信息。 闩锁链包括具有与第二芯片相关联的单个或多个闩锁的第二闩锁链。 第二锁存链被构造成从第二芯片读取数据信息。 第一锁存链和第二锁存链彼此连接，使得形成跨越码片边界的单个锁存链。 第一锁存链和第二锁存链被构造成分别提供用于识别第一芯片和第二芯片的识别信息。
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7.发明申请STRUCTURE AND METHOD FOR MONITORING STRESS INDUCED FAILURES IN INTERLEVEL DIELECTRIC LAYERS OF SOLDER BUMP INTEGRATED CIRCUITS 有权用于监测焊接电路集成电路交互介质层应力诱发失效的结构与方法公开(公告)号：US20130292817A1
公开(公告)日：2013-11-07
申请号：US13461912
申请日：2012-05-02
CPC分类号： H01L22/34 , H01L23/49816 , H01L23/50 , H01L23/5283 , H01L23/5329 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05008 , H01L2224/05073 , H01L2224/05124 , H01L2224/0554 , H01L2224/05572 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/14515 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/15311 , H01L2924/00 , H01L2924/014 , H01L2224/05552
摘要： A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density.
摘要翻译： 一种用于监测层间介电应力损伤的结构和方法。 该结构包括一个监测焊锡凸块和一般焊锡凸块; 在衬底和监测焊料凸点之间的一组层叠的层间电介质层和正常的焊料凸点，一个或多个包含介电常数为2.4或更小的超低K材料的超低K电介质层; 在超低K电介质层中的监视器焊料凸块正下方的区域中的监视器结构，并且其中在监视器焊料凸块正下方的区域中的至少一个超低K电介质层中的导体密度小于规定的最小值 正常焊锡凸块下的超低K电介质层的相应区域的密度和导体密度大于规定的最小密度。
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公开(公告)号：US20130285251A1
公开(公告)日：2013-10-31
申请号：US13459785
申请日：2012-04-30
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/768 , H01L23/5226 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure comprises a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.
摘要翻译： 集成电路结构包括形成层叠结构的多个绝缘体层（彼此连接）。 进一步包括在每个绝缘体层内的开口，以及通孔开口内的导电通孔材料。 相邻绝缘体层的对应的通孔内的导电通孔材料电连接以形成通过层压结构的顶表面和底表面之间的绝缘体层的连续的电通路。 在每个连续的电通路中，通孔相对于彼此定位，以形成通过层压结构的导电过孔材料的对角线结构路径。 相邻绝缘体层的相应通孔开始部分重叠。 对角结构路径与顶面和底面非垂直。
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公开(公告)号：US20130049834A1
公开(公告)日：2013-02-28
申请号：US13219084
申请日：2011-08-26
IPC分类号： H03K3/00
CPC分类号： H01L23/50 , G11C11/4072 , H01L25/0657 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2924/0002 , H03K3/00 , H01L2924/00
摘要： Methods and structures are provided for packaging identically processed chips in a stacked structure. A latch chain includes a first latch chain, having a single or multiple latches, associated with a first chip. The first latch chain is structured to read data information from the first chip. The latch chain includes a second latch chain, having a single or multiple latches, associated with a second chip. The second latch chain is structured to read data information from the second chip. The first latch chain and the second latch chain are connected to one another such that form a single latch chain that crosses chip boundaries. The first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.
摘要翻译： 提供了用于在堆叠结构中包装相同处理的芯片的方法和结构。 闩锁链包括与第一芯片相关联的具有单个或多个闩锁的第一闩锁链。 第一锁存链被构造成从第一芯片读取数据信息。 闩锁链包括具有与第二芯片相关联的单个或多个闩锁的第二闩锁链。 第二锁存链被构造成从第二芯片读取数据信息。 第一锁存链和第二锁存链彼此连接，使得形成跨越码片边界的单个锁存链。 第一锁存链和第二锁存链被构造成分别提供用于识别第一芯片和第二芯片的识别信息。
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10.发明授权Circuit for detecting structural defects in an integrated circuit chip, methods of use and manufacture and design structures 有权用于检测集成电路芯片中的结构缺陷的电路，使用和制造方法以及设计结构公开(公告)号：US09057760B2
公开(公告)日：2015-06-16
申请号：US13010057
申请日：2011-01-20
申请人： Luke D. Lacroix , Mark C. H. Lamorey , Steven F. Oakland , Janak G. Patel , Kerry P. Pfarr , Peter Slota, Jr. , David B. Stone
发明人： Luke D. Lacroix , Mark C. H. Lamorey , Steven F. Oakland , Janak G. Patel , Kerry P. Pfarr , Peter Slota, Jr. , David B. Stone
CPC分类号： G01R31/2884 , G01R31/2896 , H01L21/76895 , H01L22/32
摘要： Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.
摘要翻译： 本文提供了检测电路，使用和制造方法以及设计结构。 该结构包括穿过集成电路的一个或多个金属层的至少一个信号线。 电路耦合到所述至少一个信号线，其被构造为接收具有来自至少一个信号线的已知信号或来自不同电位的信号的信号，并且基于哪个信号被接收，确定是否存在 集成电路中的结构缺陷。
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