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    Bi-CMOS circuit
    3.
    发明授权
    Bi-CMOS circuit 失效
    双CMOS电路

    公开(公告)号：US5661429A

    公开(公告)日：1997-08-26

    申请号：US423613

    申请日：1995-04-17

    申请人： Takao Nakajima ,  Takayuki Harima ,  Makoto Segawa

    发明人： Takao Nakajima ,  Takayuki Harima ,  Makoto Segawa

    IPC分类号： H01L27/06 ,  H01L21/8249 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02 ,  H03K17/16 ,  H03K17/60

    CPC分类号： H03K19/0136 ,  H03K19/09448

    摘要： A BiCMOS circuit includes a CMOS circuit for inverting data applied to an input terminal and a first bipolar transistor, having a base connected to an output point of this CMOS circuit, a collector connected to a power supply voltage and an emitter connected to an output terminal, for charging the output terminal. The BiCMOS circuit also includes a second bipolar transistor, having a collector connected to the output terminal, for discharging the output terminal, a first MOS transistor of a first conductivity type connected in parallel between the base and the collector of the second bipolar transistor and a second MOS transistor of the first conductivity type connected in series with the first MOS transistor and having a gate connected to an output point of the CMOS circuit. The Bi-CMOS circuit further includes a third MOS transistor of the first conductivity type connected between the input terminal and the gate of the first MOS transistor of the first conductivity type and having a gate receiving a first reference voltage, and a fourth MOS transistor of a second conductivity type connected between the first reference voltage and the gate of the first MOS transistor. A large variation width of an output voltage can be ensured, and hence the Bi-CMOS circuit normally operates even at a low voltage without any deterioration in terms of delay time.

    摘要翻译： BiCMOS电路包括用于将施加到输入端子的数据反相的CMOS电路和具有连接到该CMOS电路的输出点的基极，连接到电源电压的集电极和连接到输出端子的发射极的第一双极晶体管 ，用于对输出端子充电。 BiCMOS电路还包括第二双极晶体管，其具有连接到输出端子的集电极，用于对输出端子进行放电，第一导电类型的第一MOS晶体管并联连接在第二双极晶体管的基极和集电极之间， 所述第一导电类型的第二MOS晶体管与所述第一MOS晶体管串联连接，并且具有连接到所述CMOS电路的输出点的栅极。 Bi-CMOS电路还包括连接在第一导电类型的第一MOS晶体管的输入端和栅极之间的第一导电类型的第三MOS晶体管，并具有接收第一参考电压的栅极，以及第四MOS晶体管 连接在第一参考电压和第一MOS晶体管的栅极之间的第二导电类型。 可以确保输出电压的大的变化幅度，因此即使在低电压下，Bi-CMOS电路也能正常工作，而且延迟时间方面没有任何劣化。

    Semiconductor memory device capable of relieving defective bits
    4.
    发明授权
    Semiconductor memory device capable of relieving defective bits 失效
    能够消除有缺陷的位置的半导体存储器件

    公开(公告)号：US5097448A

    公开(公告)日：1992-03-17

    申请号：US405885

    申请日：1989-09-11

    申请人： Makoto Segawa

    发明人： Makoto Segawa

    IPC分类号： G11C5/14 ,  G11C11/41 ,  G11C11/412 ,  G11C29/00 ,  H01L21/82 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

    CPC分类号： G11C29/78 ,  G11C11/41 ,  G11C11/412 ,  G11C29/832 ,  G11C5/14 ,  H01L27/1104

    摘要： A memory cell array includes static memory cells arranged in an array of n rows.times.m columns. Each of the memory cells includes MOS transistors formed in a semicondutor substrate and in a corresponding one of well regions of the conductivity type opposite to that of the semiconductor substrate. The well regions are independently formed for each row or for every two or more rows of the memory cell array. The well regions are connected to the respective sources of MOS transistors formed in the well regions. The source and backgate of each of the MOS transistors formed in the well regions are connected to the common source wirings for each of the independently formed well regions. Isolation circuits are respectively connected between the common source wirings for the repective well regions and the power source. A row of the memory cell array to which a defective memory cell is connected is isolated from the power source by means of the isolation circuits.

    Inverter circuit provided with gate protection
    5.
    发明授权
    Inverter circuit provided with gate protection 失效
    逆变电路提供栅极保护

    公开(公告)号：US4578694A

    公开(公告)日：1986-03-25

    申请号：US429183

    申请日：1982-09-30

    申请人： Shoji Ariizumi ,  Makoto Segawa

    发明人： Shoji Ariizumi ,  Makoto Segawa

    IPC分类号： H03K19/0944 ,  H01L27/02 ,  H01L27/088 ,  H02H9/04 ,  H03K19/003 ,  H01L27/04 ,  H01L29/78 ,  H03K17/08 ,  H03K17/687

    CPC分类号： H01L27/0883 ,  H01L27/0251 ,  H03K19/00315 ,  H01L2924/0002 ,  H02H9/046

    摘要： An integrated circuit serving as an E/D type inverter circuit and provided with a gate-protection circuit. The inverter circuit is constructed of an E type MOSFET having a gate coupled to an input signal and a D type MOSFET which operates as load, and the gate-protective circuit is constructed by a MOSFET which is connected between a power supply and the D type MOSFET and whose gate is connected to the power supply. The gate of the D type MOSFET is protected by the gate-protection circuit even if noise exists on the power supply line.

    摘要翻译： 作为E / D型逆变器电路的集成电路，具有栅极保护电路。 逆变器电路由具有耦合到输入信号的栅极的E型MOSFET和作为负载工作的D型MOSFET构成，栅极保护电路由连接在电源和D型之间的MOSFET构成 MOSFET，其栅极连接到电源。 即使电源线上存在噪声，D型MOSFET的栅极也受到栅极保护电路的保护。

    Static bootstrap semiconductor drive circuit
    6.
    发明授权
    Static bootstrap semiconductor drive circuit 失效
    静态自举半导体驱动电路

    公开(公告)号：US4554469A

    公开(公告)日：1985-11-19

    申请号：US469631

    申请日：1983-02-25

    申请人： Makoto Segawa ,  Shoji Ariizumi

    发明人： Makoto Segawa ,  Shoji Ariizumi

    IPC分类号： G11C11/413 ,  G11C8/10 ,  G11C8/18 ,  G11C11/418 ,  H03K5/02 ,  H03K17/06 ,  H03K19/094

    CPC分类号： G11C11/418 ,  G11C8/10 ,  G11C8/18

    摘要： A semiconductor circuit has a static bootstrap circuit, which includes a first MOS transistor with an input signal supplied to the gate and having the current path connected between a voltage source terminal and a node, a second MOS transistor having the gate connected to receive an inverted form of the input signal after a delay time and having the current path connected between the node and a reference potential terminal and a capacitor connected between the gate of the first MOS transistor and the node. The semiconductor circuit also has a short pulse generator. The bootstrap circuit further includes a third MOS transistor having the current path connected between the output terminal of the short pulse generator and the node and with the input signal supplied to the gate and fourth and fifth MOS transistors having the respective gates connected to the gates of the first and second MOS transistors and the respective current paths connected in series between the voltage source terminal and reference potential terminal.

    摘要翻译： 半导体电路具有静态自举电路，其包括第一MOS晶体管，其具有提供给栅极的输入信号，并且具有连接在电压源端子和节点之间的电流路径;第二MOS晶体管，其栅极连接以接收反相 在延迟时间之后输入信号的形式，并且连接在节点和参考电位端之间的电流路径以及连接在第一MOS晶体管的栅极和节点之间的电容器。 半导体电路还具有短脉冲发生器。 自举电路还包括第三MOS晶体管，其具有连接在短脉冲发生器的输出端和节点之间的电流路径以及提供给栅极的输入信号，以及连接到栅极的第四和第五MOS晶体管， 第一和第二MOS晶体管和各个电流路径串联连接在电压源端子和参考电位端子之间。

    Semiconductor device having protective and test circuits
    9.
    发明授权
    Semiconductor device having protective and test circuits 失效
    具有保护和测试电路的半导体器件

    公开(公告)号：US06442009B1

    公开(公告)日：2002-08-27

    申请号：US09604720

    申请日：2000-06-28

    申请人： Yasushi Kameda ,  Makoto Segawa

    发明人： Yasushi Kameda ,  Makoto Segawa

    IPC分类号： H02H900

    CPC分类号： G11C29/50 ,  H02H9/046

    摘要： A semiconductor device has an internal circuit (2), a PAD, a NMOS Tr (QN) as a protective transistor formed between a node (N) on a signal line and a first power source (Vss), and a NOR gate (G1) as a logical gate connected to a gate as a control terminal of the NMOS transistor (QN). The internal circuit (2) is connected to the PAD through the signal line. The NOR gate (G1) keeps the protective transistor (QN) an OFF state during a normal operation of the internal circuit (2). In addition, the semiconductor device further includes a test circuit (21). The output from the NOR gate (G1), whose one input is the output from the test circuit (21), is supplied to the gate of the NMOS transistor (QN). The output from the test circuit (21) is thereby output to outside through the NMOS transistor (QN) and the PAD.

    摘要翻译： 半导体器件具有形成在信号线上的节点（N）和第一电源（Vss）之间的作为保护晶体管的内部电路（2），PAD，NMOS Tr（QN）以及NOR门（G1） ）作为连接到作为NMOS晶体管（QN）的控制端的栅极的逻辑栅极。 内部电路（2）通过信号线连接到PAD。 NOR门（G1）在内部电路（2）的正常工作期间保持保护晶体管（QN）为OFF状态。 另外，半导体器件还包括测试电路（21）。 来自测试电路（21）的输出端的NOR门（G1）的输出被提供给NMOS晶体管（QN）的栅极。 因此，测试电路（21）的输出通过NMOS晶体管（QN）和PAD输出到外部。

    Semiconductor device and SRAM having plural power supply voltages
    10.
    发明授权
    Semiconductor device and SRAM having plural power supply voltages 失效
    具有多个电源电压的半导体器件和SRAM

    公开(公告)号：US5825707A

    公开(公告)日：1998-10-20

    申请号：US882393

    申请日：1997-07-10

    申请人： Yasumitsu Nozawa ,  Kenichi Nakamura ,  Takayuki Otani ,  Makoto Segawa

    发明人： Yasumitsu Nozawa ,  Kenichi Nakamura ,  Takayuki Otani ,  Makoto Segawa

    IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/407 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/11 ,  G11C7/00

    CPC分类号： G11C5/14 ,  G11C5/145

    摘要： A semiconductor device comprises: a first circuit (11) formed in a first well (N-type) and a second well (P-type) of a semiconductor substrate, supplied with a first supply voltage (V.sub.ss) and a second supply voltage (V.sub.cc) higher than the first supply voltage, and activated when a first well bias voltage (V.sub.BP1) is applied to the first well (N-type) and a second well bias voltage (V.sub.BN1) is applied to the second well (P-type); a second circuit (201; 202) formed in a third well (N-type) and a fourth well (P-type) of the same semiconductor substrate as above, supplied with the first supply voltage (V.sub.ss) and a third supply voltage (V.sub.cc2) higher than the first supply voltage but different from the second supply voltage (V.sub.cc), and activated when a third well bias voltage (V.sub.BP2) is applied to the third well (N-type) and a fourth well bias voltage (V.sub.BN2) is applied to the fourth well (P-type); a first bias circuit (20) supplied with the first and second supply voltages (V.sub.ss and V.sub.cc), for generating and outputting the first well bias voltage (V.sub.BP1); a second bias circuit (21) supplied with the first and second supply voltages (V.sub.ss and V.sub.cc), for generating and outputting the second well bias voltage (V.sub.BN1); a third bias circuit (16) supplied with the first and third supply voltages (V.sub.ss and V.sub.cc2) for generating and outputting the third well bias voltage (V.sub.BP2); and a fourth bias circuit (17) supplied with the first and third supply voltages (V.sub.ss and V.sub.cc2) for generating and outputting the fourth well bias voltage (V.sub.BN2). In the semiconductor device, even if any of the second supply voltage (V.sub.cc) and the third supply voltage (V.sub.cc2) is first supplied, it is possible to prevent the latch-up phenomenon caused by the floated substrate potential.

    摘要翻译： 半导体器件包括：形成在半导体衬底的第一阱（N型）和第二阱（P型）中的第一电路，被提供有第一电源电压（Vss）和第二电源电压（ Vcc）高于第一电源电压，并且当第一阱偏压（VBP1）施加到第一阱（N型）并且第二阱偏置电压（VBN1）施加到第二阱（P型）时被激活 ）; 形成在与上述相同的半导体衬底的第三阱（N型）和第四阱（P型）中的第二电路（201; 202）被提供有第一电源电压（Vss）和第三电源电压 Vcc2）高于第一电源电压但不同于第二电源电压（Vcc），并且当第三阱偏压（VBP2）施加到第三阱（N型）和第四阱偏置电压（VBN2）时被激活， 应用于第四井（P型）; 提供有第一和第二电源电压（Vss和Vcc）的第一偏置电路（20），用于产生和输出第一阱偏置电压（VBP1）; 提供有第一和第二电源电压（Vss和Vcc）的第二偏置电路（21），用于产生和输出第二阱偏置电压（VBN1）; 提供有用于产生和输出第三阱偏置电压（VBP2）的第一和第三电源电压（Vss和Vcc2）的第三偏置电路（16）; 以及第四偏置电路（17），其被提供有用于产生和输出第四阱偏置电压（VBN2）的第一和第三电源电压（Vss和Vcc2）。 在半导体装置中，即使首先提供第二电源电压（Vcc）和第三电源电压（Vcc2）中的任何一个，也可以防止浮置的基板电位引起的闭锁现象。