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公开(公告)号：US20200091093A1
公开(公告)日：2020-03-19
申请号：US16450266
申请日：2019-06-24
摘要： An electronic device and associated methods are disclosed. In one example, the electronic device includes a first device and a second device coupled to a surface of a substrate, and a continuous flexible shield woven over the first device and under the second device to separate the first device from the second device. In selected examples, the continuous flexible shield may be formed from a laminate and one or more of the devices may be coupled through an opening or via in the continuous flexible shield.
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公开(公告)号：US20190148269A1
公开(公告)日：2019-05-16
申请号：US16018635
申请日：2018-06-26
IPC分类号： H01L23/498 , H01L23/00 , H01L21/768
摘要： A fold in a semiconductor package substrate includes an embedded device that includes orthogonal electrical coupling through the package substrate by a bond-pad via that is configured to couple to a semiconductive device that is mounted on the semiconductor package substrate. The semiconductive device is coupled to the embedded device with the orthogonal electrical coupling.
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公开(公告)号：US20160148866A1
公开(公告)日：2016-05-26
申请号：US14555124
申请日：2014-11-26
申请人： Khang Choong Yong , Bok Eng Cheah , Teong Keat Beh , Howard L. Heck , Jackson Chung Peng Kong , Stephen H. Hall , Kooi Chi Ooi
发明人： Khang Choong Yong , Bok Eng Cheah , Teong Keat Beh , Howard L. Heck , Jackson Chung Peng Kong , Stephen H. Hall , Kooi Chi Ooi
IPC分类号： H01L23/528 , H01L21/768 , H01L21/288 , H01L23/00
CPC分类号： H01L21/2885 , H01L21/76802 , H01L21/76879 , H01L23/48 , H01L23/49822 , H01L23/49838 , H01L23/5383 , H01L24/13 , H01L2224/1302 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01L2924/00
摘要： Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a trench formed into one surface of the dielectric layer and a signal conductor that fills the trench and extends above the one surface of dielectric layer. The electrical interconnect further includes a conductive reference layer mounted on an opposing side of the dielectric layer. The conductive reference layer is electromagnetically coupled to the signal conductor when current passes through the signal conductor.
摘要翻译： 一些示例形式涉及电子封装的电互连。 电互连包括介电层，其包括形成在电介质层的一个表面中的沟槽和填充沟槽并在电介质层的一个表面上方延伸的信号导体。 电互连还包括安装在电介质层的相对侧上的导电参考层。 当电流通过信号导体时，导电参考层与信号导体电磁耦合。
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公开(公告)号：US20180192509A1
公开(公告)日：2018-07-05
申请号：US15396181
申请日：2016-12-30
申请人： Wil Choon Song , Khang Choong Yong , Min Suet Lim , Eng Huat Goh , Boon Ping Koh
发明人： Wil Choon Song , Khang Choong Yong , Min Suet Lim , Eng Huat Goh , Boon Ping Koh
CPC分类号： H01P3/082 , H01P3/026 , H01P3/08 , H01P3/10 , H01P5/12 , H01P11/003 , H05K1/024 , H05K1/0242 , H05K1/0243 , H05K1/0245 , H05K2201/09254
摘要： Various embodiments disclosed relate to a circuit. The circuit includes a transceiver adapted to generate a signal. A stranded transmission line is connected to the transceiver. The signal is then transmitted through the first pair of conductive strands.
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公开(公告)号：US20170290154A1
公开(公告)日：2017-10-05
申请号：US15089303
申请日：2016-04-01
CPC分类号： H05K1/147 , G06K9/0002 , H01L25/18 , H05K1/0218 , H05K1/181 , H05K3/363 , H05K9/0024 , H05K2201/047 , H05K2201/056 , H05K2201/10159
摘要： Three-dimensional (3-D) volumetric board architectural design provides technical solutions to technical problems facing miniaturization of circuit boards. The 3-D volumetric architecture includes using more of the unused volume in the vertical dimension (e.g., Z-dimension) to increase the utilization of the total circuit board volume. The 3-D volumetric architecture is realized by mounting components on a first PCB and on a second PCB, and inverting and suspending the second PCB above the first PCB. The use of 3-D volumetric board architectural design further enables formation of a shielded FEMIE, providing shielding and improved volumetric use with little or no reduction in system performance or increase in system Z-height.
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公开(公告)号：US20170185102A1
公开(公告)日：2017-06-29
申请号：US14998067
申请日：2015-12-24
IPC分类号： G06F1/16 , H01R13/10 , H01R13/426 , H01R12/70
CPC分类号： G06F1/163 , A41D1/005 , G06F1/1656 , H01R4/58 , H01R12/7011 , H01R12/718 , H05K1/11 , H05K3/4007 , H05K2201/09027
摘要： Various embodiments are generally directed to an apparatus, method and other techniques to provide a interface component including a housing comprising a first shell portion and a second shell portion, the first shell portion forming an extended portion for the housing and comprising a retention track engageable a counterpart retention track. The interface component to include a printed circuit board disposed within the housing, the printed circuit board comprising a plurality of contact pins each comprising a contact hole and a retention bump and a socket to couple with a stud.
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公开(公告)号：US20170188461A1
公开(公告)日：2017-06-29
申请号：US14757984
申请日：2015-12-26
申请人： Chee Ling Wong , Wil Choon Song , Khang Choong Yong , Eng Huat Goh , Mohd Muhaiyiddin Bin Abdullah , Tin Poay Chuah
发明人： Chee Ling Wong , Wil Choon Song , Khang Choong Yong , Eng Huat Goh , Mohd Muhaiyiddin Bin Abdullah , Tin Poay Chuah
CPC分类号： H05K1/117 , H05K1/0298 , H05K1/142 , H05K2201/09845
摘要： A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.
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公开(公告)号：US20200314999A1
公开(公告)日：2020-10-01
申请号：US16368221
申请日：2019-03-28
IPC分类号： H05K1/02 , G05B19/4097 , H05K3/02
摘要： Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
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