公开(公告)号：US20180192509A1

公开(公告)日：2018-07-05

申请号：US15396181

申请日：2016-12-30

申请人： Wil Choon Song ,  Khang Choong Yong ,  Min Suet Lim ,  Eng Huat Goh ,  Boon Ping Koh

发明人： Wil Choon Song ,  Khang Choong Yong ,  Min Suet Lim ,  Eng Huat Goh ,  Boon Ping Koh

IPC分类号： H05K1/02 ,  H01P3/08 ,  H01P11/00

CPC分类号： H01P3/082 ,  H01P3/026 ,  H01P3/08 ,  H01P3/10 ,  H01P5/12 ,  H01P11/003 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0243 ,  H05K1/0245 ,  H05K2201/09254

摘要： Various embodiments disclosed relate to a circuit. The circuit includes a transceiver adapted to generate a signal. A stranded transmission line is connected to the transceiver. The signal is then transmitted through the first pair of conductive strands.

公开(公告)号：US20170188461A1

公开(公告)日：2017-06-29

申请号：US14757984

申请日：2015-12-26

申请人： Chee Ling Wong ,  Wil Choon Song ,  Khang Choong Yong ,  Eng Huat Goh ,  Mohd Muhaiyiddin Bin Abdullah ,  Tin Poay Chuah

发明人： Chee Ling Wong ,  Wil Choon Song ,  Khang Choong Yong ,  Eng Huat Goh ,  Mohd Muhaiyiddin Bin Abdullah ,  Tin Poay Chuah

IPC分类号： H05K1/14 ,  H05K1/02 ,  H05K3/46 ,  H05K1/11 ,  H05K3/36

CPC分类号： H05K1/117 ,  H05K1/0298 ,  H05K1/142 ,  H05K2201/09845

摘要： A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

公开(公告)号：US20200091093A1

公开(公告)日：2020-03-19

申请号：US16450266

申请日：2019-06-24

申请人： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

发明人： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

IPC分类号： H01L23/60 ,  H01L23/48

摘要： An electronic device and associated methods are disclosed. In one example, the electronic device includes a first device and a second device coupled to a surface of a substrate, and a continuous flexible shield woven over the first device and under the second device to separate the first device from the second device. In selected examples, the continuous flexible shield may be formed from a laminate and one or more of the devices may be coupled through an opening or via in the continuous flexible shield.

公开(公告)号：US20170290154A1

公开(公告)日：2017-10-05

申请号：US15089303

申请日：2016-04-01

申请人： Khang Choong Yong ,  Stephen H. Hall ,  Tin Poay Chuah ,  Boon Ping Koh ,  Eng Huat Goh

发明人： Khang Choong Yong ,  Stephen H. Hall ,  Tin Poay Chuah ,  Boon Ping Koh ,  Eng Huat Goh

IPC分类号： H05K1/14 ,  H01L25/18 ,  H05K3/30 ,  H05K1/02 ,  H05K3/36 ,  H05K1/18 ,  H05K9/00

CPC分类号： H05K1/147 ,  G06K9/0002 ,  H01L25/18 ,  H05K1/0218 ,  H05K1/181 ,  H05K3/363 ,  H05K9/0024 ,  H05K2201/047 ,  H05K2201/056 ,  H05K2201/10159

摘要： Three-dimensional (3-D) volumetric board architectural design provides technical solutions to technical problems facing miniaturization of circuit boards. The 3-D volumetric architecture includes using more of the unused volume in the vertical dimension (e.g., Z-dimension) to increase the utilization of the total circuit board volume. The 3-D volumetric architecture is realized by mounting components on a first PCB and on a second PCB, and inverting and suspending the second PCB above the first PCB. The use of 3-D volumetric board architectural design further enables formation of a shielded FEMIE, providing shielding and improved volumetric use with little or no reduction in system performance or increase in system Z-height.

公开(公告)号：US20170086298A1

公开(公告)日：2017-03-23

申请号：US14863380

申请日：2015-09-23

申请人： Tin Poay Chuah ,  Min Suet Lim ,  Ping Ping Ooi ,  Eng Huat Goh ,  See Chin Chow

发明人： Tin Poay Chuah ,  Min Suet Lim ,  Ping Ping Ooi ,  Eng Huat Goh ,  See Chin Chow

IPC分类号： H05K1/18 ,  H05K3/32 ,  H05K3/30 ,  H05K1/11 ,  H05K3/00

CPC分类号： H05K1/183 ,  H01L2224/14 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/141 ,  H05K1/181 ,  H05K3/4697 ,  H05K2201/10015 ,  H05K2201/10159 ,  H05K2201/10734

摘要： Techniques and mechanisms to provide interconnect structures of a substrate such as a printed circuit board. In an embodiment, a first side of a substrate has disposed thereon a hardware interface contacts to couple the substrate to a packaged IC device. The contacts define a footprint area, where an overlap region of the substrate is defined by a projection of the footprint area from the first side to a second side of the substrate. The substrate forms a recess extending from one of the first side and the second side. In another embodiment, at least part of the recess is within the overlap region, and interconnect structures of the substrate facilitate connection between the packaged IC device and a capacitor disposed at least partially in the recess. Positioning of the capacitor within the overlap region enables improvements in substrate space efficiency, power delivery and/or signal noise.

公开(公告)号：US20190035761A1

公开(公告)日：2019-01-31

申请号：US16049790

申请日：2018-07-30

申请人： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

发明人： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L21/56

摘要： Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a second die disposed on a first die, a first plurality of interconnect structures disposed on a top surface of the first die, and a second plurality of interconnect structures disposed on a top surface of the second die. Top surfaces of the first plurality of interconnect structures are coplanar with top surfaces of the plurality of the second interconnect structures. At least one of the interconnect structures of the first or the second plurality of interconnect structures comprises a sigmoid shape.

公开(公告)号：US20190148310A1

公开(公告)日：2019-05-16

申请号：US16018940

申请日：2018-06-26

申请人： Kean Huat Leong ,  Chun Kit See ,  Sheng Jian Darren Tan ,  Paik Wen Ong ,  Eng Huat Goh

发明人： Kean Huat Leong ,  Chun Kit See ,  Sheng Jian Darren Tan ,  Paik Wen Ong ,  Eng Huat Goh

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/48

摘要： A semiconductor package substrate has a cavity on the land side among the ball-grid array, and a support structure inserted into the cavity as well as covering at least one device that is seated on the land side. The cavity is an enclave or an exclave. The support structure takes on several useful compositions as well as shapes and sizes.

公开(公告)号：US09257368B2

公开(公告)日：2016-02-09

申请号：US13996839

申请日：2012-05-14

申请人： Eng Huat Goh ,  Hoay Tien Teoh

发明人： Eng Huat Goh ,  Hoay Tien Teoh

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/50 ,  H01L23/00 ,  H01L23/29 ,  H01L23/538

CPC分类号： H01L24/02 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/0105 ,  H01L2224/05552 ,  H01L2924/00

摘要： A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

摘要翻译： 一种微电子封装，其具有邻近微电子器件的有源表面和侧面的第一无凸起的构建层结构和邻近微电子器件的后表面的第二无扰动积聚层结构，其中通过第一无扰动构建形成导电路径 从微电子器件有源表面到第二无扰性积聚层结构中的导电路径的上层，并且其中邻近微电子器件背表面并延伸到微电子器件中的穿硅通孔电连接到第二无扰动积聚层 结构导电路线。

公开(公告)号：US20140021635A1

公开(公告)日：2014-01-23

申请号：US13996839

申请日：2012-05-14

申请人： Eng Huat Goh ,  Hoay Tien Teoh

发明人： Eng Huat Goh ,  Hoay Tien Teoh

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L24/02 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/0105 ,  H01L2224/05552 ,  H01L2924/00

摘要： A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

摘要翻译： 一种微电子封装，其具有邻近微电子器件的有源表面和侧面的第一无凸起的构建层结构和邻近微电子器件的后表面的第二无扰动积聚层结构，其中通过第一无扰动构建形成导电路径 从微电子器件有源表面到第二无扰性积聚层结构中的导电路径的上层，并且其中邻近微电子器件背表面并延伸到微电子器件中的穿硅通孔电连接到第二无扰动积聚层 结构导电路线。

公开(公告)号：US20210098352A1

公开(公告)日：2021-04-01

申请号：US16912653

申请日：2020-06-25

申请人： Jiun Hann Sir ,  Eng Huat Goh ,  Poh Boon Khoo

发明人： Jiun Hann Sir ,  Eng Huat Goh ,  Poh Boon Khoo

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/552

摘要： A molded frame interconnect includes power, ground and signal frame interconnects in a molded mass, that encloses an integrated-circuit package precursor, which is inserted into the frame, and coupled to the frame interconnects by a build-up redistribution layer.