公开(公告)号：US08386992B2

公开(公告)日：2013-02-26

申请号：US13310217

申请日：2011-12-02

申请人： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

发明人： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC分类号： G06F17/50

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

摘要： A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

摘要翻译： 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下，与仅在一侧具有存储器接口电路的半导体板相比，可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此，微型计算机在主板和模块板上简化了线路设计。

公开(公告)号：US20110127671A1

公开(公告)日：2011-06-02

申请号：US13023401

申请日：2011-02-08

申请人： Yasuhiro Yoshikawa ,  Motoo Suwa ,  Kazuyuki Sakata

发明人： Yasuhiro Yoshikawa ,  Motoo Suwa ,  Kazuyuki Sakata

IPC分类号： H01L23/498

CPC分类号： H01L23/50 ,  G11C5/02 ,  G11C5/04 ,  G11C5/063 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/05599

摘要： There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip. With respect to an arrangement of the plurality of data system bonding pads of the data processor chip, an arrangement of the data system bonding pads to which the memory chip, coupled by the data system wiring, corresponds is made such that memory chips are disposed in an alternating sequence.

摘要翻译： 提供了一种半导体器件，其使得地址系统芯片之间的布线均衡容易，并且减少了用于连接芯片的数据系统布线之间的串扰噪声和电容耦合噪声的影响。 在模块板上安装数据处理器芯片同时访问的多个堆叠的存储器芯片。 多个存储器芯片对应的地址系统接合焊盘通常通过线耦合到模块板配线的一端的接合引线，其另一端通过导线耦合到数据处理器的地址系统接合焊盘。 数据处理器芯片的数据系统接合焊盘分别耦合到存储器芯片的数据系统焊盘。 关于数据处理器芯片的多个数据系统接合焊盘的布置，数据系统接合焊盘的布置是通过数据系统布线耦合的与存储芯片对应的数据系统焊盘，使得存储芯片被布置在 交替序列。

公开(公告)号：US07888795B2

公开(公告)日：2011-02-15

申请号：US12795637

申请日：2010-06-07

申请人： Yasuhiro Yoshikawa ,  Motoo Suwa ,  Kazuyuki Sakata

发明人： Yasuhiro Yoshikawa ,  Motoo Suwa ,  Kazuyuki Sakata

IPC分类号： H01L23/50

CPC分类号： H01L23/50 ,  G11C5/02 ,  G11C5/04 ,  G11C5/063 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/05599

摘要： There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip. With respect to an arrangement of the plurality of data system bonding pads of the data processor chip, an arrangement of the data system bonding pads to which the memory chip, coupled by the data system wiring, corresponds is made such that memory chips are disposed in an alternating sequence.

摘要翻译： 提供了一种半导体器件，其使得地址系统芯片之间的布线均衡容易，并且减少了用于连接芯片的数据系统布线之间的串扰噪声和电容耦合噪声的影响。 在模块板上安装数据处理器芯片同时访问的多个堆叠的存储器芯片。 多个存储器芯片对应的地址系统接合焊盘通常通过线耦合到模块板配线的一端的接合引线，其另一端通过导线耦合到数据处理器的地址系统接合焊盘。 数据处理器芯片的数据系统接合焊盘分别耦合到存储器芯片的数据系统焊盘。 关于数据处理器芯片的多个数据系统接合焊盘的布置，数据系统接合焊盘的布置是通过数据系统布线耦合的与存储芯片对应的数据系统焊盘，使得存储芯片被布置在 交替序列。

公开(公告)号：US20070194433A1

公开(公告)日：2007-08-23

申请号：US10592948

申请日：2004-03-19

申请人： Motoo Suwa ,  Yoshinori Miyaki ,  Toru Hayashi ,  Ryoichi Sano ,  Shigezumi Matsui ,  Takanobu Naruse ,  Takashi Sato ,  Hisashi Shiota

发明人： Motoo Suwa ,  Yoshinori Miyaki ,  Toru Hayashi ,  Ryoichi Sano ,  Shigezumi Matsui ,  Takanobu Naruse ,  Takashi Sato ,  Hisashi Shiota

IPC分类号： H01L23/12

CPC分类号： H01L23/552 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic circuit includes a first semiconductor device (4) and a second semiconductor device (3) on a mounting substrate. The mounting substrate includes a plurality of mounting substrate lines (201 to 204) which are connected in common with external terminals of a plurality of bits of the first semiconductor device and external terminals of a plurality of bits of the second semiconductor device for every bit. The mounting substrate lines have lengths thereof from the external terminals of the first semiconductor device to the external terminals of the second semiconductor device made unequal for respective bits. Assembling lines (361 to 364) which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. Here, the unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines. According to such a constitution, it is unnecessary to set lengths between the external terminals of the second semiconductor device and the connecting electrodes of the semiconductor chip equal.

摘要翻译： 电子电路包括在安装基板上的第一半导体器件（4）和第二半导体器件（3）。 安装基板包括与第一半导体器件的多个位的外部端子和第二半导体器件的多个位的外部端子共同连接的多个安装基板线（201〜204）。 安装基板线具有从第一半导体器件的外部端子到对于各个位不相等的第二半导体器件的外部端子的长度。 从第二半导体器件的外部端子到达半导体芯片的连接电极的组装线（361至364）使其长度对于各个位不相等。 这里，安装基板线的不等长度具有抵消装配线的不等长度的关系。 根据这种结构，不需要在第二半导体器件的外部端子和半导体芯片的连接电极之间设置长度相等。

公开(公告)号：US20060192282A1

公开(公告)日：2006-08-31

申请号：US11360808

申请日：2006-02-24

申请人： Motoo Suwa ,  Hikaru Ikegami ,  Takafumi Betsui

发明人： Motoo Suwa ,  Hikaru Ikegami ,  Takafumi Betsui

IPC分类号： H01L23/34

CPC分类号： H01L23/5385 ,  H01L23/50 ,  H01L23/5386 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0102 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/181 ,  H01L2924/00

摘要： A mounting board has a plurality of semiconductor memory devices operated in sync with a clock signal, and a semiconductor data processing device which access-controls the semiconductor memory devices. Layouts of data-system terminals of the semiconductor memory devices with respect to memory access terminals of the semiconductor data processing device are determined in such a manner that wirings for data and a data strobe system (RTdq/dqs) become shorter than wirings for a command/address system (RTcmd/add). The wirings for the data and data strobe system (RTdq/dqs) are laid down using an area defined between the semiconductor memory devices. The wirings for the command/address system (RTcmd/add) bypass the side of the mounting board.

摘要翻译： 安装板具有与时钟信号同步操作的多个半导体存储器件，以及访问控制半导体存储器件的半导体数据处理器件。 确定半导体存储器件相对于半导体数据处理器件的存储器访问端子的数据系统端子的布局，使得数据布线和数据选通系统（RTdq / dqs）变得比命令布线短 /地址系统（RTcmd / add）。 数据和数据选通系统（RTdq / dqs）的布线使用半导体存储器件之间定义的区域进行布局。 命令/地址系统（RTcmd / add）的布线绕过安装板侧面。

公开(公告)号：US09390766B2

公开(公告)日：2016-07-12

申请号：US13372425

申请日：2012-02-13

申请人： Yasuhiro Yoshikawa ,  Motoo Suwa ,  Kazuhiko Hiranuma

发明人： Yasuhiro Yoshikawa ,  Motoo Suwa ,  Kazuhiko Hiranuma

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  H01L2224/32225 ,  H01L2224/48465 ,  H01L2224/73265

摘要： There is a need to provide a semiconductor device and an electronic device capable of easily allowing a bypass capacitor to always improve noise suppression on a signal path in order to transmit a reference potential between chips in different power supply noise states. There is provided a specified signal path that connects a control chip and a memory chip mounted on a mounting substrate and transmits a reference potential generated from the control chip. A bypass capacitor is connected to the specified signal path only at a connecting part where a distance from a reference potential pad of the memory chip to the connecting part along the specified signal path is shorter than a distance from a reference potential pad of the control chip to the connecting part along the specified signal path.

摘要翻译： 需要提供能够容易地允许旁路电容器总是改善信号路径上的噪声抑制的半导体器件和电子器件，以便以不同的电源噪声状态在芯片之间传输参考电位。 提供了连接控制芯片和安装在安装基板上的存储芯片的指定信号路径，并传输从控制芯片产生的参考电位。 旁路电容器仅在连接部分处连接到指定的信号路径，在连接部分处，沿着指定信号路径的存储芯片的参考电位焊盘到连接部分的距离短于距控制芯片的参考电位焊盘的距离 沿着指定的信号路径连接到连接部分。

公开(公告)号：US07888788B2

公开(公告)日：2011-02-15

申请号：US12860415

申请日：2010-08-20

申请人： Yasuhiro Yoshikawa ,  Motoo Suwa ,  Hiroshi Toyoshima

发明人： Yasuhiro Yoshikawa ,  Motoo Suwa ,  Hiroshi Toyoshima

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/528 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/05599

摘要： Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other. A major signal wiring of an external output system connected to the external output terminal, which may be a noise source, is made to be in a wiring layer distant from the semiconductor integrated circuit.

摘要翻译： 从外部输出信号系统到能够并联输入/输出操作的外部输入信号系统的互感减小。 半导体集成电路具有面向封装基板的多个外部连接端子，具有能够并行输入/输出操作的外部输入端子和外部输出端子作为外部连接端子的一部分。 封装基板具有用于将外部连接端子和彼此对应的模块端子之间电连接的多个布线层。 面向半导体集成电路的第一布线层具有用于连接外部输入端子和彼此对应的模块端子之间的主要布线，并且其中形成模块端子的第二布线层具有用于连接外部 输出端子和对应的模块端子。 连接到可能是噪声源的外部输出端子的外部输出系统的主要信号布线被制成在远离半导体集成电路的布线层中。

公开(公告)号：US20100314761A1

公开(公告)日：2010-12-16

申请号：US12860415

申请日：2010-08-20

申请人： Yasuhiro Yoshikawa ,  Motoo Suwa ,  Hiroshi Toyoshima

发明人： Yasuhiro Yoshikawa ,  Motoo Suwa ,  Hiroshi Toyoshima

IPC分类号： H01L23/498

CPC分类号： H01L23/528 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/05599

摘要： Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other. A major signal wiring of an external output system connected to the external output terminal, which may be a noise source, is made to be in a wiring layer distant from the semiconductor integrated circuit.

摘要翻译： 从外部输出信号系统到能够并联输入/输出操作的外部输入信号系统的互感减小。 半导体集成电路具有面向封装基板的多个外部连接端子，具有能够并行输入/输出操作的外部输入端子和外部输出端子作为外部连接端子的一部分。 封装基板具有用于将外部连接端子和彼此对应的模块端子之间电连接的多个布线层。 面向半导体集成电路的第一布线层具有用于连接外部输入端子和彼此对应的模块端子之间的主要布线，并且其中形成模块端子的第二布线层具有用于连接外部 输出端子和对应的模块端子。 连接到可能是噪声源的外部输出端子的外部输出系统的主要信号布线被制成在远离半导体集成电路的布线层中。

公开(公告)号：US20070192559A1

公开(公告)日：2007-08-16

申请号：US11616966

申请日：2006-12-28

申请人： Takafumi BETSUI ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

发明人： Takafumi BETSUI ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC分类号： G06F13/00

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

摘要： A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

摘要翻译： 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下，与仅在一侧具有存储器接口电路的半导体板相比，可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此，微型计算机在主板和模块板上简化了线路设计。

公开(公告)号：US20050258532A1

公开(公告)日：2005-11-24

申请号：US11135297

申请日：2005-05-24

申请人： Yasuhiro Yoshikawa ,  Motoo Suwa ,  Hiroaki Nambu

发明人： Yasuhiro Yoshikawa ,  Motoo Suwa ,  Hiroaki Nambu

IPC分类号： H01L23/12 ,  H01L23/04 ,  H01L23/498 ,  H01L29/40 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11

CPC分类号： H01L23/49838 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10674 ,  H01L2924/00012

摘要： A wiring board includes a plurality of wiring layers, and one surface formed with a plurality of chip connecting electrodes and another surface formed with a plurality of external connecting electrodes of a semiconductor device. The wiring board has wiring layers and vias. The plurality of chip connecting electrodes include first chip connecting electrodes, each used for a first signal whose logic value changes, and second chip connecting electrodes, each used for a second signal that changes after a change timing of the first signal. A wiring layer in which wiring routing of paths extending from the first chip connecting electrodes to their corresponding first external connecting electrodes is performed, and a wiring layer in which wiring routing of paths extending from the second chip connecting electrodes disposed adjacent to the first chip connecting electrodes to their corresponding second external connecting electrodes is performed, are made different from each other.

摘要翻译： 布线板包括多个布线层，一个表面形成有多个芯片连接电极，另一个表面形成有多个半导体器件的外部连接电极。 接线板具有接线层和通孔。 多个芯片连接电极包括第一芯片连接电极，每个用于其逻辑值改变的第一信号，第二芯片连接电极用于在第一信号的改变定时之后改变的第二信号。 执行从第一芯片连接电极延伸到其对应的第一外部连接电极的路径的布线布线的布线层，以及布线层，其中从邻近第一芯片连接的第二芯片连接电极延伸的路径布线 执行到它们对应的第二外部连接电极的电极彼此不同。