公开(公告)号：US20070194433A1

公开(公告)日：2007-08-23

申请号：US10592948

申请日：2004-03-19

申请人： Motoo Suwa ,  Yoshinori Miyaki ,  Toru Hayashi ,  Ryoichi Sano ,  Shigezumi Matsui ,  Takanobu Naruse ,  Takashi Sato ,  Hisashi Shiota

发明人： Motoo Suwa ,  Yoshinori Miyaki ,  Toru Hayashi ,  Ryoichi Sano ,  Shigezumi Matsui ,  Takanobu Naruse ,  Takashi Sato ,  Hisashi Shiota

IPC分类号： H01L23/12

CPC分类号： H01L23/552 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic circuit includes a first semiconductor device (4) and a second semiconductor device (3) on a mounting substrate. The mounting substrate includes a plurality of mounting substrate lines (201 to 204) which are connected in common with external terminals of a plurality of bits of the first semiconductor device and external terminals of a plurality of bits of the second semiconductor device for every bit. The mounting substrate lines have lengths thereof from the external terminals of the first semiconductor device to the external terminals of the second semiconductor device made unequal for respective bits. Assembling lines (361 to 364) which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. Here, the unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines. According to such a constitution, it is unnecessary to set lengths between the external terminals of the second semiconductor device and the connecting electrodes of the semiconductor chip equal.

摘要翻译： 电子电路包括在安装基板上的第一半导体器件（4）和第二半导体器件（3）。 安装基板包括与第一半导体器件的多个位的外部端子和第二半导体器件的多个位的外部端子共同连接的多个安装基板线（201〜204）。 安装基板线具有从第一半导体器件的外部端子到对于各个位不相等的第二半导体器件的外部端子的长度。 从第二半导体器件的外部端子到达半导体芯片的连接电极的组装线（361至364）使其长度对于各个位不相等。 这里，安装基板线的不等长度具有抵消装配线的不等长度的关系。 根据这种结构，不需要在第二半导体器件的外部端子和半导体芯片的连接电极之间设置长度相等。

公开(公告)号：US07528473B2

公开(公告)日：2009-05-05

申请号：US10592948

申请日：2004-03-19

申请人： Motoo Suwa ,  Yoshinori Miyaki ,  Toru Hayashi ,  Ryoichi Sano ,  Shigezumi Matsui ,  Takanobu Naruse ,  Takashi Sato ,  Hisashi Shiota

发明人： Motoo Suwa ,  Yoshinori Miyaki ,  Toru Hayashi ,  Ryoichi Sano ,  Shigezumi Matsui ,  Takanobu Naruse ,  Takashi Sato ,  Hisashi Shiota

IPC分类号： H01L23/52

CPC分类号： H01L23/552 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic circuit includes a first semiconductor device and a second semiconductor device on a mounting substrate. The mounting substrate lines have lengths which are made unequal for respective bits. Assembling lines which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. The unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines.

摘要翻译： 电子电路包括第一半导体器件和安装基板上的第二半导体器件。 安装衬底线的长度对于各个位而言是不相等的。 从第二半导体器件的外部端子到达半导体芯片的连接电极的组装线使其长度对于各个位不相等。 安装基板线的不等长度具有抵消组装线的不等长度的关系。

公开(公告)号：US07412616B2

公开(公告)日：2008-08-12

申请号：US10895394

申请日：2004-07-21

申请人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

发明人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

IPC分类号： H04L7/00

CPC分类号： G06F13/4243 ,  G06F13/1689

摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

摘要翻译： 存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。 时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。 存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样 通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。

公开(公告)号：US07945801B2

公开(公告)日：2011-05-17

申请号：US12169853

申请日：2008-07-09

申请人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

发明人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

IPC分类号： H04L7/00

CPC分类号： G06F13/4243 ,  G06F13/1689

摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

摘要翻译： 存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。 时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。 存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样 通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。

公开(公告)号：US20050047192A1

公开(公告)日：2005-03-03

申请号：US10895394

申请日：2004-07-21

申请人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

发明人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G06F15/78 ,  G11C11/22 ,  G11C11/401 ,  G11C11/407

CPC分类号： G06F13/4243 ,  G06F13/1689

摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

摘要翻译： 存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。 时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。 存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样 通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。

公开(公告)号：US20070192559A1

公开(公告)日：2007-08-16

申请号：US11616966

申请日：2006-12-28

申请人： Takafumi BETSUI ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

发明人： Takafumi BETSUI ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC分类号： G06F13/00

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

摘要： A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

摘要翻译： 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下，与仅在一侧具有存储器接口电路的半导体板相比，可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此，微型计算机在主板和模块板上简化了线路设计。

公开(公告)号：US08581302B2

公开(公告)日：2013-11-12

申请号：US13295053

申请日：2011-11-12

申请人： Mitsuya Kinoshita ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

发明人： Mitsuya Kinoshita ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

IPC分类号： H01L27/118

CPC分类号： H01L27/0207 ,  H01L24/02 ,  H01L27/11898 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/14131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014

摘要： Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other.

摘要翻译： 从具有并行驱动器配置的I / O缓冲器输出的信号稳定可靠性提高。 每个I / O单元具有互补I / O单元，其输出一个输出信号作为由非反相信号和反相信号组成的互补信号。 两个I / O单元并联耦合。 第一反相器的输出部分通过第一布线耦合在一起; 并且第二反相器的输出部分通过第二布线耦合在一起。 第一布线形成在I / O单元的下侧，使得它跨越两个I / O单元，并且第二布线形成在第一布线之上，使得它跨越两个I / O单元。 布置布线使得第一布线的布线长度和第二布线的布线长度基本相等。

公开(公告)号：US20120126403A1

公开(公告)日：2012-05-24

申请号：US13295053

申请日：2011-11-12

申请人： Mitsuya KINOSHITA ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

发明人： Mitsuya KINOSHITA ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

IPC分类号： H01L23/498

CPC分类号： H01L27/0207 ,  H01L24/02 ,  H01L27/11898 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/14131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014

摘要： Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other.

摘要翻译： 从具有并行驱动器配置的I / O缓冲器输出的信号稳定可靠性提高。 每个I / O单元具有互补I / O单元，其输出一个输出信号作为由非反相信号和反相信号组成的互补信号。 两个I / O单元并联耦合。 第一反相器的输出部分通过第一布线耦合在一起; 并且第二反相器的输出部分通过第二布线耦合在一起。 第一布线形成在I / O单元的下侧，使得它跨越两个I / O单元，并且第二布线形成在第一布线之上，使得它跨越两个I / O单元。 布置布线使得第一布线的布线长度和第二布线的布线长度基本相等。

公开(公告)号：US08091061B2

公开(公告)日：2012-01-03

申请号：US11616966

申请日：2006-12-28

申请人： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

发明人： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC分类号： G06F17/50

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

摘要： A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

摘要翻译： 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下，与仅在一侧具有存储器接口电路的半导体板相比，可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此，微型计算机在主板和模块板上简化了线路设计。

公开(公告)号：US08386992B2

公开(公告)日：2013-02-26

申请号：US13310217

申请日：2011-12-02

申请人： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

发明人： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC分类号： G06F17/50

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

摘要： A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

摘要翻译： 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下，与仅在一侧具有存储器接口电路的半导体板相比，可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此，微型计算机在主板和模块板上简化了线路设计。