公开(公告)号：US08866202B2

公开(公告)日：2014-10-21

申请号：US13457147

申请日：2012-04-26

申请人： S. M. Reza Sadjadi ,  Zhi-Song Huang

发明人： S. M. Reza Sadjadi ,  Zhi-Song Huang

IPC分类号： H01L21/70 ,  H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L23/482 ,  H01L21/033 ,  H01L21/311

CPC分类号： H01L21/7682 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L23/4821 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.

摘要翻译： 提供一种降低半导体器件之间的电容的方法。 在电介质层中形成多个接触结构。 形成掩模以覆盖接触结构，其中掩模具有用于暴露电介质层的部分的掩模特征，其中掩模特征具有宽度。 掩模特征的宽度随着侧壁沉积而收缩。 间隙通过侧壁沉积蚀刻到介电层中。 间隙封闭以形成间隙中的凹坑。

公开(公告)号：US08614149B2

公开(公告)日：2013-12-24

申请号：US13586571

申请日：2012-08-15

申请人： Sangheon Lee ,  Dae-Han Choi ,  Jisoo Kim ,  Peter Cirigliano ,  Zhisong Huang ,  Robert Charatan ,  S. M. Reza Sadjadi

发明人： Sangheon Lee ,  Dae-Han Choi ,  Jisoo Kim ,  Peter Cirigliano ,  Zhisong Huang ,  Robert Charatan ,  S. M. Reza Sadjadi

IPC分类号： H01L21/311

CPC分类号： C23F4/00 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816 ,  Y10S438/947

摘要： A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.

摘要翻译： 提供了一种在蚀刻层中形成特征的方法。 在蚀刻层上形成光致抗蚀剂层。 图案化光致抗蚀剂层以形成具有光致抗蚀剂侧壁的光致抗蚀剂特征。 在光致抗蚀剂层和光致抗蚀剂特征的底部上形成控制层。 在光致抗蚀剂特征和控制层的侧壁上沉积保形层以减少光刻胶特征的临界尺寸。 控制层的开口打开，控制层突破性化学。 特征被蚀刻到蚀刻层中，其蚀刻化学性质不同于控制层突破化学，其中控制层比蚀刻化学性质比保形层蚀刻更耐腐蚀。

公开(公告)号：US08361564B2

公开(公告)日：2013-01-29

申请号：US12339514

申请日：2008-12-19

申请人： Andrew R. Romano ,  S. M. Reza Sadjadi

发明人： Andrew R. Romano ,  S. M. Reza Sadjadi

IPC分类号： C23C14/04 ,  C23C14/14 ,  C23C14/00

CPC分类号： H01L21/266 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/26513

摘要： A method for implanting a dopant in a substrate is provided. A patterned photoresist mask is formed over the substrate, wherein the patterned photoresist mask has patterned photoresist mask features. A protective layer is deposited on the patterned photoresist mask by performing a cyclical deposition, wherein each cycle, comprises a depositing phase for depositing a deposition layer over surfaces of the patterned mask of photoresist material and a profile shaping phase for providing vertical sidewalls. A dopant is implanted into the substrate using an ion beam. The protective layer and photoresist mask are removed.

摘要翻译： 提供了一种用于在衬底中注入掺杂剂的方法。 图案化的光致抗蚀剂掩模形成在衬底上，其中图案化的光刻胶掩模具有图案化的光刻胶掩模特征。 通过执行循环沉积，在图案化的光致抗蚀剂掩模上沉积保护层，其中每个循环包括用于在光致抗蚀剂材料的图案化掩模的表面上沉积沉积层的沉积相和用于提供垂直侧壁的轮廓成形阶段。 使用离子束将掺杂剂注入到衬底中。 去除保护层和光刻胶掩模。

公开(公告)号：US20120298301A1

公开(公告)日：2012-11-29

申请号：US13572061

申请日：2012-08-10

申请人： Tamarak Pandhumsoporn ,  Patrick Chung ,  Jackie Seto ,  S. M. Reza Sadjadi

发明人： Tamarak Pandhumsoporn ,  Patrick Chung ,  Jackie Seto ,  S. M. Reza Sadjadi

IPC分类号： C23F1/08

CPC分类号： H01L21/3086 ,  H01L21/31138

摘要： A method for forming features in a silicon layer is provided. A mask is formed with a plurality of mask openings over the silicon layer. A polymer layer is deposited over the mask by flowing a hydrogen free deposition gas comprising C4F8, forming a plasma from the deposition gas, depositing a polymer from the plasma for at least 20 seconds, and stopping the depositing the polymer after the at least 20 seconds. The deposited polymer layer is opened by flowing an opening gas, forming a plasma from the opening gas which selectively removes the deposited polymer on bottoms of the plurality of mask openings with respect to deposited polymer on sides of the plurality of mask openings, and stopping the opening when at least some of the plurality of mask features are opened. The silicon layer is etched through the mask and deposited polymer layer.

摘要翻译： 提供了一种在硅层中形成特征的方法。 在硅层上形成有多个掩模开口的掩模。 通过使包含C4F8的无氢沉积气体从沉积气体形成等离子体，从等离子体沉积聚合物至少20秒，并在至少20秒后停止沉积聚合物，沉积聚合物层 。 沉积的聚合物层通过流动开口气体而打开，从开口气体形成等离子体，其在多个掩模开口的侧面上相对于沉积的聚合物选择性地去除多个掩模开口的底部上沉积的聚合物，并且停止 当多个掩模特征中的至少一些被打开时打开。 通过掩模蚀刻硅层并沉积聚合物层。

公开(公告)号：US08187412B2

公开(公告)日：2012-05-29

申请号：US12341568

申请日：2008-12-22

申请人： S. M. Reza Sadjadi ,  Zhi-Song Huang

发明人： S. M. Reza Sadjadi ,  Zhi-Song Huang

IPC分类号： C23F1/00 ,  H01L21/306 ,  C23C16/00

CPC分类号： H01L21/7682 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L23/4821 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.

摘要翻译： 提供一种用于降低半导体器件之间的电容的方法。 在电介质层中形成多个接触结构。 形成掩模以覆盖接触结构，其中掩模具有用于暴露电介质层的部分的掩模特征，其中掩模特征具有宽度。 掩模特征的宽度随着侧壁沉积而收缩。 间隙通过侧壁沉积蚀刻到介电层中。 间隙封闭，形成缝隙。

公开(公告)号：US20090286397A1

公开(公告)日：2009-11-19

申请号：US12121711

申请日：2008-05-15

申请人： S. M. Reza Sadjadi

发明人： S. M. Reza Sadjadi

IPC分类号： H01L21/44 ,  C23C16/00

CPC分类号： C23C16/45523 ,  C23C16/505 ,  H01J37/321 ,  H01J37/3244 ,  H01J37/32449 ,  H01L21/0337 ,  H01L21/32139

摘要： An inductively coupled power (ICP) plasma processing chamber for forming semiconductor features is provided. A plasma processing chamber is provided, comprising a vacuum chamber, at least one antenna adjacent to the vacuum chamber for providing inductively coupled power in the vacuum chamber, a substrate support for supporting a silicon substrate within the plasma processing chamber, a pressure regulator, a gas inlet for providing gas into the plasma processing chamber, and a gas outlet for exhausting gas from the plasma processing chamber. A gas distribution system is in fluid connection with the gas inlet for providing a first gas and a second gas, wherein the gas distribution system can substantially replace one of the first gas and the second gas in the plasma zone with the other of the first gas and the second gas within a period of less than 5 seconds.

摘要翻译： 提供一种用于形成半导体特征的电感耦合功率（ICP）等离子体处理室。 提供了一种等离子体处理室，包括真空室，与真空室相邻的至少一个天线，用于在真空室中提供电感耦合功率，用于在等离子体处理室内支撑硅衬底的衬底支架，压力调节器， 用于向等离子体处理室提供气体的气体入口和用于从等离子体处理室排出气体的气体出口。 气体分配系统与气体入口流体连接，用于提供第一气体和第二气体，其中气体分配系统可以基本上替换等离子体区域中的第一气体和第二气体中的另一个，而第一气体 和第二气体在小于5秒的时间内。

公开(公告)号：US20090163035A1

公开(公告)日：2009-06-25

申请号：US12339511

申请日：2008-12-19

申请人： Andrew R. Romano ,  S. M. Reza Sadjadi

发明人： Andrew R. Romano ,  S. M. Reza Sadjadi

IPC分类号： H01L21/3065 ,  C23F1/08

CPC分类号： H01L21/31144 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： A method for etching features into an etch layer is provided. A patterned mask is formed over the etch layer, wherein the patterned mask is of a high etch rate photoresist material, wherein the patterned mask has patterned mask features. A protective layer is deposited on the patterned mask of high etch rate photoresist material by performing a cyclical deposition, wherein each cycle, comprises a depositing phase for depositing a deposition layer over the exposed surfaces, including sidewalls of the patterned mask of high etch rate photoresist material and a profile shaping phase for providing vertical sidewalls. Features are etched into the etch layer using the protective layer as a mask. The protective layer is removed.

摘要翻译： 提供了将特征蚀刻到蚀刻层中的方法。 图案化掩模形成在蚀刻层上，其中图案化掩模是高蚀刻速率光致抗蚀剂材料，其中图案化掩模具有图案化掩模特征。 通过执行循环沉积，保护层沉积在高蚀刻速率光致抗蚀剂材料的图案化掩模上，其中每个循环包括沉积相，用于在暴露表面上沉积沉积层，包括高蚀刻速率光致抗蚀剂的图案化掩模的侧壁 材料和用于提供垂直侧壁的轮廓成形阶段。 使用保护层作为掩模将特征蚀刻到蚀刻层中。 保护层被去除。

公开(公告)号：US20090140380A1

公开(公告)日：2009-06-04

申请号：US12341568

申请日：2008-12-22

申请人： S. M. Reza Sadjadi ,  Zhi-Song Huang

发明人： S. M. Reza Sadjadi ,  Zhi-Song Huang

IPC分类号： H01L23/532 ,  H01L21/20

CPC分类号： H01L21/7682 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L23/4821 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.

摘要翻译： 提供一种降低半导体器件之间的电容的方法。 在电介质层中形成多个接触结构。 形成掩模以覆盖接触结构，其中掩模具有用于暴露电介质层的部分的掩模特征，其中掩模特征具有宽度。 掩模特征的宽度随着侧壁沉积而收缩。 间隙通过侧壁沉积蚀刻到介电层中。 间隙封闭以形成间隙中的凹坑。

公开(公告)号：US07465525B2

公开(公告)日：2008-12-16

申请号：US11126466

申请日：2005-05-10

申请人： S. M. Reza Sadjadi ,  Nicolas Bright

发明人： S. M. Reza Sadjadi ,  Nicolas Bright

IPC分类号： G03F9/00

CPC分类号： H01L21/0338 ,  G03F7/70433 ,  G03F7/70466

摘要： A method for generating a plurality of reticle layouts is provided. A feature layout with a feature layout pitch is received. A plurality of reticle layouts is generated from the feature layout where each reticle layout of the plurality of reticle layouts has a reticle layout pitch and where each reticle layout pitch is at least twice the feature layout pitch.

摘要翻译： 提供了一种用于产生多个标线布局的方法。 接收具有特征布局间距的特征布局。 从特征布局生成多个标线布局，其中多个标线布局的每个标线布局具有标线布局间距，并且其中每个标线布局间距至少是特征布局间距的两倍。

公开(公告)号：US07405521B2

公开(公告)日：2008-07-29

申请号：US10645665

申请日：2003-08-22

申请人： Raj Dhindsa ,  S. M. Reza Sadjadi ,  Felix Kozakevich ,  Dave Trussell ,  Lumin Li ,  Eric Lenz ,  Camelia Rusu ,  Mukund Srinivasan ,  Aaron Eppler ,  Jim Tietz ,  Jeffrey Marks

发明人： Raj Dhindsa ,  S. M. Reza Sadjadi ,  Felix Kozakevich ,  Dave Trussell ,  Lumin Li ,  Eric Lenz ,  Camelia Rusu ,  Mukund Srinivasan ,  Aaron Eppler ,  Jim Tietz ,  Jeffrey Marks

IPC分类号： H01J7/24 ,  C23F1/00 ,  C23C16/00

CPC分类号： H01J37/32174 ,  H01J37/32082 ,  H01J37/32165

摘要： A workpiece is processed with a plasma in a vacuum plasma processing chamber by exciting the plasma at several frequencies such that the excitation of the plasma by the several frequencies simultaneously causes several different phenomena to occur in the plasma. The chamber includes central top and bottom electrodes and a peripheral top and/or bottom electrode arrangement that is either powered by RF or is connected to a reference potential by a filter arrangement that passes at least one of the plasma excitation frequencies to the exclusion of other frequencies.

摘要翻译： 通过以几个频率激发等离子体，在真空等离子体处理室中用等离子体处理工件，使得等离子体被几个频率激发同时导致在等离子体中发生几种不同的现象。 该腔室包括中央顶部和底部电极以及由RF供电的外围顶部和/或底部电极装置，或通过将至少一个等离子体激发频率传递至排除另一个等离子体激发频率的滤波器装置连接到参考电位 频率