公开(公告)号：US08374024B2

公开(公告)日：2013-02-12

申请号：US12982996

申请日：2010-12-31

Applicant: Tae Hun Yoon ,  Dong Keun Kim

Inventor： Tae Hun Yoon ,  Dong Keun Kim

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071

Abstract: A semiconductor memory apparatus includes a memory cell, a data transfer unit configured to adjust an access to the memory cell according to a voltage level of a selection signal, a selection signal output unit configured to output the selection signal having a first control voltage level in a data write mode and a second control voltage level in a data read mode. A data detection unit may also be configured to detect a voltage formed by a sensing current supplied to the memory cell through the data transfer unit in the data read mode, and output read data according to the detection result, wherein the second control voltage level is lower than the first control voltage level.

Abstract translation: 一种半导体存储装置，包括存储单元，数据传送单元，被配置为根据选择信号的电压来调整对存储单元的访问;选择信号输出单元，被配置为输出具有第一控制电压电平的选择信号 数据写入模式和第二控制电压电平。 数据检测单元还可以被配置为在数据读取模式中检测通过数据传送单元提供给存储单元的感测电流形成的电压，并且根据检测结果输出读取数据，其中第二控制电压电平为 低于第一控制电压电平。

公开(公告)号：US08416601B2

公开(公告)日：2013-04-09

申请号：US12641200

申请日：2009-12-17

Applicant: Tae Hun Yoon

Inventor： Tae Hun Yoon

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C7/1039 ,  G11C7/18 ,  G11C11/5678 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2207/002

Abstract: A phase change memory apparatus includes: a plurality of sub blocks; a latch block connected in common with the sub blocks through a read bus and configured to latch data from one of the sub blocks; and a comparator connected in common with the sub blocks to receive data from a write bus, and configured to compare data of the latch block with the data of the write bus to generate a comparison signal, which is effective in improving areal efficiency by sharing the latch block among the sub blocks in the unit mat.

Abstract translation: 相变存储装置包括：多个子块; 锁存块，其通过读总线与子块共同连接，并被配置为锁存来自子块之一的数据; 以及与子块共用的比较器，用于从写总线接收数据，并且被配置为将锁存块的数据与写总线的数据进行比较，以生成比较信号，该比较信号通过共享 单元垫子块中的锁存块。

公开(公告)号：US20120051127A1

公开(公告)日：2012-03-01

申请号：US12982996

申请日：2010-12-31

Applicant: Tae Hun YOON ,  Dong Keun KIM

Inventor： Tae Hun YOON ,  Dong Keun KIM

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0071

Abstract: A semiconductor memory apparatus includes a memory cell, a data transfer unit configured to adjust an access to the memory cell according to a voltage level of a selection signal, a selection signal output unit configured to output the selection signal having a first control voltage level in a data write mode and a second control voltage level in a data read mode. A data detection unit may also be configured to detect a voltage formed by a sensing current supplied to the memory cell through the data transfer unit in the data read mode, and output read data according to the detection result, wherein the second control voltage level is lower than the first control voltage level.

Abstract translation: 一种半导体存储装置，包括存储单元，数据传送单元，被配置为根据选择信号的电压来调整对存储单元的访问;选择信号输出单元，被配置为输出具有第一控制电压电平的选择信号 数据写入模式和第二控制电压电平。 数据检测单元还可以被配置为在数据读取模式中检测通过数据传送单元提供给存储单元的感测电流形成的电压，并且根据检测结果输出读取数据，其中第二控制电压电平为 低于第一控制电压电平。

公开(公告)号：US08027189B2

公开(公告)日：2011-09-27

申请号：US12487731

申请日：2009-06-19

Applicant: Tae-Hun Yoon ,  Hyuck-Soo Yoon

Inventor： Tae-Hun Yoon ,  Hyuck-Soo Yoon

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C8/08 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078

Abstract: A nonvolatile memory device includes a plurality of programming current driving units configured to supply memory cells with a programming current corresponding to a write data, a common programming current controlling unit configured to generate a common control voltage for controlling the programming current and a switching unit configured to transfer the common control voltage to the programming current driving unit selected among the plurality of programming current driving units by a plurality of driving selection signals.

Abstract translation: 一种非易失性存储器件包括：多个编程电流驱动单元，被配置为向存储单元提供与写数据相对应的编程电流;公共编程电流控制单元，被配置为产生用于控制编程电流的公共控制电压;以及配置 通过多个驱动选择信号将公共控制电压传送到在多个编程电流驱动单元中选择的编程电流驱动单元。

公开(公告)号：US20120170360A1

公开(公告)日：2012-07-05

申请号：US13343399

申请日：2012-01-04

Applicant: Tae Hun YOON

Inventor： Tae Hun YOON

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C7/04 ,  G11C7/1096 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device converts a sequentially-changing step voltage into a current so as to provide a write current, and minimizes the influence of a threshold voltage variation caused by fabrication deviation, such that it can be stably operated. The semiconductor memory device includes a current driver. The current driver includes a step voltage provider configured to provide a step control voltage sequentially changing in response to a pulse control signal, a control current provider configured to provide a control current in response to the step control voltage, and a write driver configured to provide a write current capable of writing data in a memory cell in response to the control current.

Abstract translation: 公开了一种半导体存储器件。 半导体存储器件将顺序变化的阶跃电压转换为电流以提供写入电流，并且使得由制造偏差引起的阈值电压变化的影响最小化，使得其可以稳定地工作。 半导体存储器件包括电流驱动器。 当前驱动器包括步进电压提供器，其被配置为响应于脉冲控制信号提供顺序变化的步进控制电压，控制电流提供器被配置为响应于步进控制电压提供控制电流;以及写入驱动器，被配置为提供 能够响应于控制电流在存储器单元中写入数据的写入电流。

公开(公告)号：US08049325B2

公开(公告)日：2011-11-01

申请号：US12472725

申请日：2009-05-27

Applicant: Shin Mu-Seob ,  Tae-Hun Kim ,  Min-Gi Hong ,  Shin Kim ,  Tae-Hun Yoon

Inventor： Shin Mu-Seob ,  Tae-Hun Kim ,  Min-Gi Hong ,  Shin Kim ,  Tae-Hun Yoon

IPC: H01L23/538

CPC classification number: H01L23/13 ,  H01L23/49816 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: An integrated circuit substrate includes an integrated circuit chip having a plurality of electrically conductive pads on a surface thereof and a printed circuit board mounted to the integrated circuit chip. The printed circuit board includes an alternating arrangement of first and second electrically conductive bond fingers. These first and second bond fingers are elevated at first and second different heights, respectively, relative to the plurality of electrically conductive pads. The printed circuit board also includes a first plurality of electrically insulating pedestals supporting respective ones of the first electrically conductive bond fingers at elevated heights relative to the second electrically conductive bond fingers. First and second pluralities of electrical interconnects (e.g., wires, beam leads) are also provided. The first plurality of electrical interconnects operate to electrically connect first ones of the plurality of electrically conductive pads to respective ones of the first electrically conductive bond fingers. The second plurality of electrical interconnects electrically connect second ones of the plurality of electrically conductive pads to respective ones of the second electrically conductive bond fingers.

Abstract translation: 集成电路基板包括在其表面上具有多个导电焊盘的集成电路芯片和安装到集成电路芯片的印刷电路板。 印刷电路板包括第一和第二导电键合指状物的交替布置。 这些第一和第二粘结指相对于多个导电垫分别在第一和第二不同的高度处升高。 印刷电路板还包括第一多个电绝缘基座，其相对于第二导电粘合指状件在升高的高度处支撑相应的第一导电键合指状物。 还提供了第一和第二多个电互连（例如，电线，光束引线）。 第一多个电互连操作以将多个导电焊盘中的第一个导电焊盘电连接到相应的第一导电焊接指状物。 所述第二多个电互连将所述多个导电焊盘中的第二导电焊盘电连接到所述第二导电焊接指中的相应导电焊盘。

公开(公告)号：US20100302840A1

公开(公告)日：2010-12-02

申请号：US12641200

申请日：2009-12-17

Applicant: Tae Hun YOON

Inventor： Tae Hun YOON

IPC: G11C11/00 ,  G11C8/00 ,  G11C7/10

CPC classification number: G11C13/0004 ,  G11C7/1039 ,  G11C7/18 ,  G11C11/5678 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2207/002

Abstract: A phase change memory apparatus includes: a plurality of sub blocks; a latch block connected in common with the sub blocks through a read bus and configured to latch data from one of the sub blocks; and a comparator connected in common with the sub blocks to receive data from a write bus, and configured to compare data of the latch block with the data of the write bus to generate a comparison signal, which is effective in improving areal efficiency by sharing the latch block among the sub blocks in the unit mat.

Abstract translation: 相变存储装置包括：多个子块; 锁存块，其通过读总线与子块共同连接，并被配置为锁存来自子块之一的数据; 以及与子块共用的比较器，用于从写总线接收数据，并且被配置为将锁存块的数据与写总线的数据进行比较，以生成比较信号，该比较信号通过共享 单元垫子块中的锁存块。

公开(公告)号：US08139427B2

公开(公告)日：2012-03-20

申请号：US12488653

申请日：2009-06-22

Applicant: Tae-Hun Yoon ,  Joo-Ae Lee

Inventor： Tae-Hun Yoon ,  Joo-Ae Lee

IPC: G11C7/00

CPC classification number: G11C7/062 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2207/063

Abstract: A nonvolatile memory device includes a data sense amplifier configured to supply a data detection current to a memory cell and detect a data detection voltage having a voltage level corresponding to a resistance of the memory cell, a first switching element configured to selectively transfer the data detection current to the memory cell, and a second switching element configured to be turned on simultaneously with the first switching element to selectively transfer the data detection current to the memory cell. The first switching element and the second switching element have a complementary voltage transfer characteristic.

Abstract translation: 非易失性存储器件包括：数据读出放大器，被配置为向存储单元提供数据检测电流，并检测具有与存储单元的电阻对应的电压电平的数据检测电压;第一开关元件，被配置为选择性地传输数据检测 以及第二开关元件，其被配置为与第一开关元件同时导通，以选择性地将数据检测电流传送到存储单元。 第一开关元件和第二开关元件具有互补电压传递特性。

公开(公告)号：US08130541B2

公开(公告)日：2012-03-06

申请号：US12650518

申请日：2009-12-30

Applicant: Dong Keun Kim ,  Tae Hun Yoon

Inventor： Dong Keun Kim ,  Tae Hun Yoon

IPC: G11C11/00

CPC classification number: G11C29/48 ,  G11C29/12005 ,  G11C29/1201

Abstract: A test circuit transfers data, which is generated by current supplied from an external source, to a memory cell in response to a test mode signal.

Abstract translation: 测试电路响应于测试模式信号将从外部源提供的电流产生的数据传送到存储器单元。

公开(公告)号：US08531892B2

公开(公告)日：2013-09-10

申请号：US13343399

申请日：2012-01-04

Applicant: Tae Hun Yoon

Inventor： Tae Hun Yoon

IPC: G11C16/04

CPC classification number: G11C7/04 ,  G11C7/1096 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device converts a sequentially-changing step voltage into a current so as to provide a write current, and minimizes the influence of a threshold voltage variation caused by fabrication deviation, such that it can be stably operated. The semiconductor memory device includes a current driver. The current driver includes a step voltage provider configured to provide a step control voltage sequentially changing in response to a pulse control signal, a control current provider configured to provide a control current in response to the step control voltage, and a write driver configured to provide a write current capable of writing data in a memory cell in response to the control current.

Abstract translation: 公开了一种半导体存储器件。 半导体存储器件将顺序变化的阶跃电压转换为电流以提供写入电流，并且使得由制造偏差引起的阈值电压变化的影响最小化，使得其可以稳定地工作。 半导体存储器件包括电流驱动器。 当前驱动器包括步进电压提供器，其被配置为响应于脉冲控制信号提供顺序变化的步进控制电压，控制电流提供器被配置为响应于步进控制电压提供控制电流;以及写入驱动器，被配置为提供 能够响应于控制电流在存储器单元中写入数据的写入电流。