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    Sealing layer of a field effect transistor
    2.
    发明授权
    Sealing layer of a field effect transistor 有权
    场效应晶体管的密封层

    公开(公告)号：US08258588B2

    公开(公告)日：2012-09-04

    申请号：US12757241

    申请日：2010-04-09

    Applicant: Yu Chao Lin ,  Jr Jung Lin ,  Yih-Ann Lin ,  Jih-Jse Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Chang

    Inventor： Yu Chao Lin ,  Jr Jung Lin ,  Yih-Ann Lin ,  Jih-Jse Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Chang

    IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238

    CPC classification number: H01L29/4983 ,  H01L29/6656

    Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

    Abstract translation: 场效应晶体管的栅极结构的示例性结构包括栅电极; 栅电极下方的栅极绝缘体，在栅电极的相对侧具有基极区域; 以及在所述栅极结构的侧壁上的密封层，其中覆盖所述基底区域的所述密封层的下部的厚度小于所述栅极电极的侧壁上的所述密封层的上部的厚度，由此所述场效应晶体管 在基板表面几乎没有凹陷。

    Method for fabricating an isolation structure
    3.
    发明授权
    Method for fabricating an isolation structure 有权
    隔离结构的制造方法

    公开(公告)号：US08163625B2

    公开(公告)日：2012-04-24

    申请号：US12753972

    申请日：2010-04-05

    Applicant: Yih-Ann Lin ,  Hao-Ming Lien ,  Ryan Chia-Jen Chen ,  Jr Jung Lin ,  Yu Chao Lin ,  Chih-Han Lin

    Inventor： Yih-Ann Lin ,  Hao-Ming Lien ,  Ryan Chia-Jen Chen ,  Jr Jung Lin ,  Yu Chao Lin ,  Chih-Han Lin

    IPC: H01L21/76

    CPC classification number: H01L21/76232

    Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure having almost no divot. An exemplary method for fabricating an isolation structure, comprising: forming a pad oxide layer over a top surface of a substrate; forming an opening in the pad oxide layer, exposing a portion of the substrate; etching the exposed portion of the substrate, forming a trench in the substrate; filling the trench with an insulator; exposing a surface of the pad oxide layer and a surface of the insulator to a vapor mixture including at least an NH3 and a fluorine-containing compound; and heating the substrate at a temperature between 100° C. to 200° C.

    Abstract translation: 本公开涉及集成电路制造，并且更具体地涉及具有几乎没有纹波的隔离结构的电子器件。 一种用于制造隔离结构的示例性方法，包括：在衬底的顶表面上形成衬垫氧化物层; 在所述衬垫氧化物层中形成开口，暴露所述衬底的一部分; 蚀刻衬底的暴露部分，在衬底中形成沟槽; 用绝缘体填充沟槽; 将衬垫氧化物层的表面和绝缘体的表面暴露于至少包含NH 3和含氟化合物的蒸汽混合物; 并在100℃至200℃的温度下加热基材。

    High-k metal gate CMOS patterning method
    5.
    发明授权
    High-k metal gate CMOS patterning method 有权
    高k金属栅极CMOS图案化方法

    公开(公告)号：US08349680B2

    公开(公告)日：2013-01-08

    申请号：US12536629

    申请日：2009-08-06

    Applicant: Kong-Beng Thei ,  Harry Chuang ,  Ryan Chia-Jen Chen ,  Su-Chen Lai ,  Yi-Shien Mor ,  Yi-Hsing Chen ,  Gary Shen ,  Yu Chao Lin

    Inventor： Kong-Beng Thei ,  Harry Chuang ,  Ryan Chia-Jen Chen ,  Su-Chen Lai ,  Yi-Shien Mor ,  Yi-Hsing Chen ,  Gary Shen ,  Yu Chao Lin

    IPC: H01L21/8238

    CPC classification number: H01L21/31645 ,  H01L21/31604 ,  H01L21/823842

    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.

    Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成覆盖层，在覆盖层上形成第一金属层 第一金属层具有第一功函数，在第一有源区中的第一金属层上形成掩模层，使用掩模层去除第一金属层和第二有源区中的覆盖层的至少一部分 并且在所述第二有源区域中的所述部分去除的覆盖层上形成第二金属层，所述第二金属层具有第二功函数。

    Patterning Methodology for Uniformity Control
    6.
    发明申请
    Patterning Methodology for Uniformity Control 有权
    均匀性控制的图案化方法

    公开(公告)号：US20120108046A1

    公开(公告)日：2012-05-03

    申请号：US13281862

    申请日：2011-10-26

    Applicant: Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

    Inventor： Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

    IPC: H01L21/28 ,  H01L21/308

    CPC classification number: H01L21/32139 ,  H01L21/0276 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/823437 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.

    Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成可图案化层。 该方法包括在可图案层上形成第一层。 该方法包括在第一层上形成第二层。 第二层比第一层薄得多。 该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。 该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。 第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。 该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。

    SEALING LAYER OF A FIELD EFFECT TRANSISTOR
    7.
    发明申请
    SEALING LAYER OF A FIELD EFFECT TRANSISTOR 有权
    密封场效应晶体管层

    公开(公告)号：US20110031562A1

    公开(公告)日：2011-02-10

    申请号：US12757241

    申请日：2010-04-09

    Applicant: Yu Chao LIN ,  Jr Jung LIN ,  Yih-Ann LIN ,  Jih-Jse LIN ,  Chao-Cheng CHEN ,  Ryan Chia-Jen CHEN ,  Weng CHANG

    Inventor： Yu Chao LIN ,  Jr Jung LIN ,  Yih-Ann LIN ,  Jih-Jse LIN ,  Chao-Cheng CHEN ,  Ryan Chia-Jen CHEN ,  Weng CHANG

    IPC: H01L29/78

    CPC classification number: H01L29/4983 ,  H01L29/6656

    Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

    Abstract translation: 场效应晶体管的栅极结构的示例性结构包括栅电极; 栅电极下方的栅极绝缘体，在栅电极的相对侧具有基极区域; 以及在所述栅极结构的侧壁上的密封层，其中覆盖所述基底区域的所述密封层的下部的厚度小于所述栅电极的侧壁上的所述密封层的上部的厚度，由此所述场效应晶体管 在基板表面几乎没有凹陷。

    Method of reducing a critical dimension of a semiconductor device
    8.
    发明授权
    Method of reducing a critical dimension of a semiconductor device 有权
    降低半导体器件临界尺寸的方法

    公开(公告)号：US07759239B1

    公开(公告)日：2010-07-20

    申请号：US12435552

    申请日：2009-05-05

    Applicant: Yu Chao Lin ,  De-Fang Chen ,  Chia-Wei Chang ,  Yih-Ann Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Cheng

    Inventor： Yu Chao Lin ,  De-Fang Chen ,  Chia-Wei Chang ,  Yih-Ann Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Cheng

    IPC: H01L21/3205

    CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144

    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate layer over a substrate, forming a hard mask layer over a gate layer, forming a first material layer over the hard mask layer, forming a patterned photoresist layer having an opening over the first material layer, etching the first material layer through a cycle including forming a second material layer over the semiconductor device and etching the first and second material layers, repeating the cycle until the hard mask layer is exposed by a reduced opening, the reduced opening formed in a last cycle, etching the hard mask layer beneath the second opening to expose the gate layer, and patterning the gate layer using the hard mask layer. An etching selectivity of the first and second material layers is smaller than an etching selectivity of the second material layer and the photoresist layer.

    Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成栅极层，在栅极层上形成硬掩模层，在硬掩模层上形成第一材料层，形成在第一材料层上具有开口的图案化光刻胶层，蚀刻第一材料 层，其包括在半导体器件上形成第二材料层并蚀刻第一和第二材料层，重复该循环，直到硬掩模层通过减小的开口暴露，在最后一个循环中形成的减小的开口，蚀刻硬 掩模层以暴露栅极层，并且使用硬掩模层图案化栅极层。 第一和第二材料层的蚀刻选择性小于第二材料层和光致抗蚀剂层的蚀刻选择性。

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