公开(公告)号：US06781783B2

公开(公告)日：2004-08-24

申请号：US10024984

申请日：2001-12-18

申请人： Yasuo Amano ,  Shigeo Nakamura ,  Osamu Narisawa ,  Mikio Tokuyama ,  Masahito Kobayashi ,  Hiroyasu Sasaki ,  Yuuji Fujita

发明人： Yasuo Amano ,  Shigeo Nakamura ,  Osamu Narisawa ,  Mikio Tokuyama ,  Masahito Kobayashi ,  Hiroyasu Sasaki ,  Yuuji Fujita

IPC分类号： G11B2102

CPC分类号： G11B5/486 ,  G11B5/4886 ,  G11B5/5565 ,  G11B21/21

摘要： Provided is a magnetic disc apparatus comprising a magnetic head for writing and reading data to and from a magnetic disc, a slider for floating up the magnetic head from the magnetic disc on rotation, a suspension having an IC chip mounting surface, for supporting the slider, a positioning mechanism for positioning a magnetic head at a predetermined position, and an IC chip mounted on the IC chip supporting surface of the suspension, wherein the rate of variation in temperature difference between opposite sides of the IC chip mounting position as a center on the IC chip mounting surface is set to be below about 3.5 K/sec. Thereby it is possible to restrain the averaged seek time for the magnetic disc from becoming longer.

摘要翻译： 提供了一种磁盘装置，包括用于向磁盘写入和读取数据的磁头，用于旋转从磁盘浮起磁头的滑块，具有IC芯片安装表面的悬架，用于支撑滑块 ，用于将磁头定位在预定位置的定位机构和安装在悬架的IC芯片支撑表面上的IC芯片，其中作为中心的IC芯片安装位置的相对侧之间的温度差的变化率 将IC芯片安装面设定为低于约3.5K / sec。 由此，可以抑制磁盘的平均寻道时间变长。

公开(公告)号：US5251100A

公开(公告)日：1993-10-05

申请号：US934330

申请日：1992-08-25

申请人： Yuuji Fujita ,  Masahide Tokuda

发明人： Yuuji Fujita ,  Masahide Tokuda

IPC分类号： H01L23/36 ,  H01L23/40 ,  H01L23/473 ,  H05K7/20

CPC分类号： H01L23/4006 ,  H01L23/473 ,  H01L2023/4043 ,  H01L2224/16225

摘要： A semiconductor integrated circuit device is equipped with a cooling system which serves to cool a plurality of integrated circuit chips mounted on a circuit board. The cooling system is kept in contact with the upper surfaces of the plurality of integrated circuit chips. A chip surface arranging plate of uniform thickness is formed with apertures smaller than the integrated circuit chips mounted on the circuit board. The cooling system is fixed on the chip surface arranging plate. The upper surfaces of the integrated circuit chips are substantially kept flush by the chip surface arranging plate. Further, the integrated circuit chips are thermally joined to the cooling system so that heat generated by the integrated circuit chips is removed by the cooling system. The plurality of integrated circuit chips are joined to the chip surface arranging plate by applying a vacuum that causes suction of air through the apertures formed in the chip surface arranging plate. Thereafter, the cooling system is fixed to the chip surface arranging plate.

摘要翻译： 半导体集成电路器件配备有用于冷却安装在电路板上的多个集成电路芯片的冷却系统。 冷却系统与多个集成电路芯片的上表面保持接触。 具有均匀厚度的芯片表面布置板形成有小于安装在电路板上的集成电路芯片的孔。 冷却系统固定在芯片表面布置板上。 集成电路芯片的上表面通过芯片表面布置板基本保持齐平。 此外，集成电路芯片被热接合到冷却系统，使得由集成电路芯片产生的热量被冷却系统去除。 多个集成电路芯片通过施加通过形成在芯片表面布置板中的孔的空气吸引的真空而接合到芯片表面布置板。 此后，将冷却系统固定到芯片表面布置板。

公开(公告)号：US5021504A

公开(公告)日：1991-06-04

申请号：US247015

申请日：1988-09-19

申请人： Yuuji Fujita ,  Tadashi Sezume ,  Kitsusho Kitano ,  Kiyotada Narukawa ,  Takashi Mikami ,  Tetsuya Kawamura ,  Shigeru Sato ,  Takeyoshi Nishio ,  Toshio Yokoi ,  Takao Nomura

发明人： Yuuji Fujita ,  Tadashi Sezume ,  Kitsusho Kitano ,  Kiyotada Narukawa ,  Takashi Mikami ,  Tetsuya Kawamura ,  Shigeru Sato ,  Takeyoshi Nishio ,  Toshio Yokoi ,  Takao Nomura

IPC分类号： C08L23/02 ,  C08L69/00

CPC分类号： C08L69/00 ,  C08L23/02

摘要： A thermoplastic resin composition having well-balanced properties which comprises 95-5 weight % of polycarbonate, 5-95 weight % of polyolefin and a particular combination of additional components selected from a styrene-ethylene.propylene copolymer, a styrene-ethylene. butyrene-styrene block copolymer, an AES resin, a styrene-olefin block copolymer, an unsaturated carboxylic acid-modified polyolefin, polybutylene terephthalate, a styrene-maleic anhydride copolymer, an oxazoline ring-containing styrene copolymer a saponified olefin-vinyl ester copolymer and an epoxy group-containing styrene copolymer.

公开(公告)号：US5870289A

公开(公告)日：1999-02-09

申请号：US572747

申请日：1995-12-14

申请人： Masahide Tokuda ,  Takeshi Kato ,  Hiroyuki Itoh ,  Masayoshi Yagyu ,  Yuuji Fujita ,  Mitsuo Usami

发明人： Masahide Tokuda ,  Takeshi Kato ,  Hiroyuki Itoh ,  Masayoshi Yagyu ,  Yuuji Fujita ,  Mitsuo Usami

IPC分类号： H01L21/60 ,  H01L21/68 ,  H01L21/98 ,  H01L23/12 ,  H01L23/28 ,  H01L23/29 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H05K1/11 ,  H05K1/18 ,  H05K3/30 ,  H05K3/32 ,  H05K3/40 ,  H05K1/14 ,  H05K1/16 ,  H05K7/02 ,  H05K7/06

CPC分类号： H01L21/6836 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/83192 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/303 ,  H05K3/4007

摘要： A structure for connecting an integrated circuit chip to a wiring substrate which implements high-density packaging, high-density connection, high-speed signal transmission, and low cost. An integrated circuit is connected to a wiring substrate by means of flip-chip die bonding using an adhesive film. A direct through-hole connection is formed directly below a connecting pad so as to pass through the adhesive film and the wiring substrate. This direct through-hole connection directly connects the connecting pad to the wire. As a result of reduced area and thickness of the chip, the chip is mounted in high density, and high-density inputs and outputs are implemented by means of minute two-dimensional connections. Short wire connections directly connected to the chip permit high speed signal transmission, and high reliability is ensured by the dispersion of stress. Low-cost packaging can be effected by simple processes and facilities.

摘要翻译： 用于将集成电路芯片连接到实现高密度封装，高密度连接，高速信号传输和低成本的布线基板的结构。 集成电路通过使用粘合膜的倒装芯片贴片连接到布线基板。 直接通孔连接形成在连接焊盘的正下方，以穿过粘合膜和布线基板。 这种直接通孔连接将连接垫直接连接到电线。 由于芯片的面积和厚度减小，芯片以高密度安装，高密度输入和输出通过微小的二维连接来实现。 直接连接到芯片的短线连接允许高速信号传输，并且通过应力分散来确保高可靠性。 低成本的包装可以通过简单的工艺和设施来实现。

公开(公告)号：US5485039A

公开(公告)日：1996-01-16

申请号：US990029

申请日：1992-12-14

申请人： Yuuji Fujita ,  Kenichi Mizuishi

发明人： Yuuji Fujita ,  Kenichi Mizuishi

IPC分类号： H01L21/60 ,  H01L23/473 ,  H01L23/498 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC分类号： H01L23/473 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15312

摘要： A semiconductor device includes a semiconductor substrate having a pair of opposed main surfaces with a wiring conductor provided on one of the main surfaces; the substrate having at least one through hole extending therethrough so as to be perpendicular to the main surfaces; at least one electrically conductive pin provided on the other of the main surfaces at a position of the at least one through hole, and an adhesive filled into the at least one through hole for fixing the at least one conductive pin to the substrate, wherein the at least one conductive pin is connected electrically through the corresponding at least one through hole to the wiring conductor to transmit/receive an electrical signal to/from an external circuit.

摘要翻译： 半导体器件包括：半导体衬底，具有一对相对的主表面，其中一个主表面上设有布线导体; 所述基板具有贯穿其中的至少一个通孔以垂直于所述主表面; 在所述至少一个通孔的位置处设置在所述主表面中的另一个表面上的至少一个导电销，以及填充到所述至少一个通孔中以将所述至少一个导电销固定到所述基板的粘合剂，其中， 至少一个导电引脚通过相应的至少一个通孔电连接到布线导体以向/从外部电路发送/接收电信号。

公开(公告)号：US5394490A

公开(公告)日：1995-02-28

申请号：US104582

申请日：1993-08-11

申请人： Takeshi Kato ,  Yuuji Fujita ,  Kenichi Mizuishi ,  Atumi Kawata ,  Hiroyuki Itoh

发明人： Takeshi Kato ,  Yuuji Fujita ,  Kenichi Mizuishi ,  Atumi Kawata ,  Hiroyuki Itoh

IPC分类号： G02B6/12 ,  G02B6/13 ,  G02B6/30 ,  G02B6/42 ,  G02B6/43 ,  G06F1/10 ,  H05K1/00

CPC分类号： G02B6/43 ,  G02B6/13 ,  G02B6/30 ,  G02B6/42 ,  G06F1/105 ,  G02B2006/12104 ,  G02B6/4232 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15312 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025

摘要： A clock signal supply system is disclosed for a semiconductor device with a semiconductor chip and a wiring substrate connected in flip-chip fashion and an optical waveguide interposed in the space between electrode members, in which the mutual arrangement of the electrical interconnection and the optical waveguide interconnection on the wiring substrate is not affected and can be used separately from each other for different applications, thereby improving the throughput of the interconnections as a whole. In order to distribute a very fast clock signal beyond a 1 GHz in particular without any phase deviation in the clock signal supply system, a clock distributor includes a clock oscillator, a phase adjuster for adjusting the phase at each destination of the clock signal, an optical interconnection for supplying the clock signal to the phase adjuster, a reference signal generator for generating a phase reference signal from the clock signal, and an electrical interconnection for supplying the reference signal to the phase adjuster. The clock signal is supplied by an optical interconnection having a broad frequency bandwidth, and the phase reference signal by an electrical interconnection by which the skew is controlled easily. A clock signal adjusted to high phase accuracy can thus be distributed to following destinations by the phase adjuster.

摘要翻译： 公开了一种半导体器件的时钟信号供给系统，半导体器件具有以倒装芯片方式连接的半导体芯片和布线基板，以及插入在电极部件之间的空间中的光波导，其中电互连和光波导 布线基板上的互连不受影响，并且可以彼此分开地用于不同的应用，从而提高互连的整体的吞吐量。 为了在非常快的时钟信号中分配非常快的时钟信号，特别是在时钟信号供给系统中没有任何相位偏差，时钟分配器包括时钟振荡器，用于调整时钟信号的每个目的地的相位的相位调节器， 用于向相位调节器提供时钟信号的光互连，用于从时钟信号产生相位参考信号的参考信号发生器和用于将参考信号提供给相位调节器的电互连。 时钟信号由具有宽频带宽的光互连提供，并且相位参考信号由通过电互连的相位参考信号提供，通过该互连可以容易地控制偏斜。 因此，调整到高相位精度的时钟信号可以由相位调节器分配到后续目的地。

公开(公告)号：US06825280B1

公开(公告)日：2004-11-30

申请号：US09485189

申请日：2000-02-07

申请人： Yu Hayakawa ,  Tsuyoshi Ogasawara ,  Yuuji Fujita ,  Masao Sakaizawa ,  Kimiho Kosegaki ,  Toshihiko Sugano ,  Takao Tayano ,  Toru Suzuki ,  Yasuo Maruyama ,  Osamu Shibata ,  Takao Usami

发明人： Yu Hayakawa ,  Tsuyoshi Ogasawara ,  Yuuji Fujita ,  Masao Sakaizawa ,  Kimiho Kosegaki ,  Toshihiko Sugano ,  Takao Tayano ,  Toru Suzuki ,  Yasuo Maruyama ,  Osamu Shibata ,  Takao Usami

IPC分类号： C08L2310

CPC分类号： C08L53/00 ,  C08F10/06 ,  C08F210/06 ,  C08F297/08 ,  C08K7/14 ,  C08L23/06 ,  C08L23/0815 ,  C08L23/10 ,  C08L23/16 ,  C08L51/06 ,  C08L2205/03 ,  C08L2314/02 ,  C08L2314/06 ,  C08L2666/06 ,  C08L2666/24 ,  C08L2666/02 ,  C08L2666/04 ,  C08F210/16 ,  C08F2500/12 ,  C08F2500/15 ,  C08F2500/03

摘要： Disclosed are a propylene polymer composition possessing excellent balance among rigidity and low warpage, resistance to deterioration caused by thermal oxidation during processing, weathering resistance, antistatic properties, and low bleeding properties, and a propylene resin composition which can easily produce molded products having excellent balance between rigidity and impact resistance (particularly low-temperature impact resistance) or heat resistance. The propylene polymer composition and the propylene resin composition comprise a propylene block copolymer consisting essentially of the following blocks (a) and (b) and having a melt flow rate of 0.1 to 200 g/10 min: block (a): a polymer block of a homopolymer of propylene or a random copolymer of propylene with a comonomer selected from the group consisting of ethylene and C4-C20 &agr;-olefins, the content of the comonomer being not more than 10% by mole; and block (b): a polymer block of a random copolymer of propylene with at least one comonomer selected from the group consisting of ethylene and C4-C20 &agr;-olefins, the content of the comonomer being 10 to 80% by mole, the average chain length of the comonomer block and the gross average chain length of the comonomer having a relationship represented by formula (I) nb≦n+1.5  (I) wherein nb represents the average chain length of the comonomer block; and n represents the gross average chain length of the comonomer.

摘要翻译： 公开了在刚性和低翘曲之间具有优异的平衡性，耐加工中的热氧化，耐候性，抗静电性和低渗透性的耐劣化性的丙烯聚合物组合物，以及可以容易地制备具有优异平衡性的模塑产品的丙烯树脂组合物 刚性和抗冲击性（特别是低温耐冲击性）或耐热性。 丙烯聚合物组合物和丙烯树脂组合物包含基本上由以下嵌段（a）和（b）组成并且熔体流动速率为0.1至200g / 10min的丙烯嵌段共聚物：嵌段（a）：聚合物嵌段 的丙烯均聚物或丙烯与选自乙烯和C 4 -C 20α-烯烃的共聚单体的无规共聚物，共聚单体的含量不超过10摩尔％ 和嵌段（b）：丙烯与至少一种选自乙烯和C 4 -C 20α-烯烃的共聚单体的无规共聚物的聚合物嵌段，共聚单体的含量为10〜80摩尔％，平均链 共聚单体嵌段的长度和由式（I）表示的关系的共聚单体的总平均链长，其中nb表示共聚单体嵌段的平均链长; n表示共聚单体的总平均链长。

公开(公告)号：US20070116075A1

公开(公告)日：2007-05-24

申请号：US11594724

申请日：2006-11-09

申请人： Yuuji Fujita ,  Makoto Sakaguchi

发明人： Yuuji Fujita ,  Makoto Sakaguchi

IPC分类号： H01S3/00 ,  H02H3/00

CPC分类号： H01S5/06213 ,  G11B7/0062 ,  G11B7/126 ,  H01S5/0427

摘要： A laser diode driver includes a DC current source supplying DC current to a laser diode, a high frequency current source connected in parallel with the DC current source and supplying high frequency current to the laser diode. The laser diode driver further includes a circuit capable of changing the current of the DC current source when the high frequency current source is operating.

摘要翻译： 激光二极管驱动器包括向激光二极管提供DC电流的DC电流源，与DC电流源并联连接并向激光二极管提供高频电流的高频电流源。 激光二极管驱动器还包括当高频电流源工作时能够改变直流电流源的电流的电路。