公开(公告)号：US12057837B2

公开(公告)日：2024-08-06

申请号：US17485226

申请日：2021-09-24

Applicant: iCometrue Company Ltd.

Inventor： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC: H03K19/1776 ,  G11C11/16 ,  G11C11/412 ,  G11C11/419 ,  G11C13/00 ,  G11C14/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H03K19/0948 ,  H03K19/173 ,  H03K19/17728 ,  H03K19/20 ,  H10B10/00 ,  H10B61/00 ,  H10B63/00 ,  H10N70/00 ,  H03K19/21

CPC classification number: H03K19/1776 ,  G11C11/1673 ,  G11C11/412 ,  G11C11/419 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/004 ,  G11C14/0081 ,  G11C14/009 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L25/18 ,  H03K19/0948 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/20 ,  H10B10/00 ,  H10B10/15 ,  H10B61/00 ,  H10B61/10 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B63/80 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8833 ,  G11C2213/15 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/83104 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H03K19/21 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/83104 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014

Abstract: A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

公开(公告)号：US20240203874A1

公开(公告)日：2024-06-20

申请号：US18406162

申请日：2024-01-07

Applicant: iCometrue Company Ltd.

Inventor： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC: H01L23/528 ,  G11C7/10 ,  G11C11/412 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/5329 ,  H01L24/17 ,  G11C7/106 ,  G11C11/412

Abstract: A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top surface of each of the plurality of through vias.

公开(公告)号：US20240056082A1

公开(公告)日：2024-02-15

申请号：US18231415

申请日：2023-08-08

Applicant: iCometrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: H03K19/173 ,  H10B80/00 ,  H01L25/04 ,  H03K3/037

CPC classification number: H03K19/173 ,  H10B80/00 ,  H01L25/043 ,  H03K3/037

Abstract: A multi-chip package includes a first semiconductor integrated-circuit (IC) chip comprising a first input/output (I/O) circuit therein; and an input/output (I/O) integrated-circuit (IC) chip comprising a second input/output (I/O) circuit therein coupling to the first input/output (I/O) circuit, a third input/output (I/O) circuit therein, a voltage-level shift-up circuit therein configured to shift data from a first voltage level at a first node thereof coupling to the second input/output (I/O) circuit to a second voltage at a second node thereof coupling to the third input/output (I/O) circuit and a voltage-level shift-down circuit therein configured to shift data from the second voltage level at the second node coupling to the third input/output (I/O) circuit to the first voltage level at the first node coupling to the second input/output (I/O) circuit, wherein the second voltage level is higher than the first voltage level.

公开(公告)号：US20230353151A1

公开(公告)日：2023-11-02

申请号：US18202916

申请日：2023-05-27

Applicant: iCometrue Company Ltd.

Inventor： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC: H03K19/0175 ,  H03K19/1776 ,  G06F30/34

CPC classification number: H03K19/017581 ,  H03K19/1776 ,  G06F30/34

Abstract: An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

公开(公告)号：US20230187365A1

公开(公告)日：2023-06-15

申请号：US17952249

申请日：2022-09-24

Applicant: iCometrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/5384 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H10B80/00 ,  H01L2225/06541

Abstract: A semiconductor IC chip comprising: a silicon substrate; a first transistor at a top surface of the silicon substrate; a first through silicon via (TSV) vertically in the silicon substrate; a second through silicon via (TSV) vertically in the silicon substrate; a first interconnection scheme on the top surface of the silicon substrate, wherein the first interconnection scheme comprises an insulating dielectric layer, a metal via in the insulating dielectric layer, a metal pad on a bottom surface of the insulating dielectric layer and a bottom surface of the metal via and coupling to the first TSV, and a first metal interconnect coupling the second TSV to the first transistor; and a second interconnection scheme on a bottom surface of the silicon substrate, wherein the second interconnection scheme comprises a second metal interconnect coupling the first TSV to the second TSV; and a first metal contact at a top of the semiconductor IC chip and on a top surface of the first interconnection scheme, wherein the first metal contact couples to the first transistor through, in sequence, the metal via, metal pad, first TSV, second metal interconnect, second TSV and first metal interconnect, wherein the first metal contact is configured for coupling to a voltage of power supply.

公开(公告)号：US11625523B2

公开(公告)日：2023-04-11

申请号：US17187766

申请日：2021-02-27

Applicant: iCometrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: G06F30/34 ,  G06F3/06 ,  H01L27/112 ,  G11C7/10 ,  H03K19/1776 ,  G05B19/042 ,  G11C11/412 ,  H03K19/177 ,  H01L25/18 ,  H01L25/16 ,  H01L27/11524

Abstract: A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

公开(公告)号：US11545477B2

公开(公告)日：2023-01-03

申请号：US17169537

申请日：2021-02-07

Applicant: iCometrue Company Ltd.

Inventor： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC: H01L25/18 ,  H01L23/498 ,  H01L21/56 ,  H03K19/17736 ,  H03K19/17796 ,  H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L23/532 ,  H01L27/118 ,  H01L23/14

Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

公开(公告)号：US20220223494A1

公开(公告)日：2022-07-14

申请号：US17571450

申请日：2022-01-08

Applicant: iCometrue Company Ltd.

Inventor： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ping-Jung Yang

IPC: H01L23/427 ,  H01L25/10 ,  H01L21/48 ,  F28D15/04

Abstract: A micro heat transfer component includes a bottom metal plate; a top metal plate; a plurality of sidewalls each having a top end joining the top metal plate and a bottom end joining the bottom metal plate, wherein the top and bottom metal plates and the sidewalls form a chamber in the micro heat transfer component; a plurality of metal posts in the chamber and between the top and bottom metal plates, wherein each of the metal posts has a top end joining the top metal plate and a bottom end joining the bottom metal plate; a metal layer in the chamber, between the top and bottom metal plates and intersecting each of the metal posts, wherein a plurality of openings are in the metal layer, wherein a first space in the chamber is between the metal layer and bottom metal plate and a second space in the chamber is between the metal layer and top metal plate; and a liquid in the first space in the chamber.

公开(公告)号：US20220149845A1

公开(公告)日：2022-05-12

申请号：US17581974

申请日：2022-01-23

Applicant: iCometrue Company Ltd.

Inventor： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC: H03K19/1776 ,  H03K19/17724 ,  H01L27/02 ,  H01L27/22 ,  H01L27/24 ,  H01L27/11517 ,  H01L23/00 ,  H01L27/12 ,  H01L43/08 ,  H01L27/092 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/66

Abstract: A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

公开(公告)号：US11159165B2

公开(公告)日：2021-10-26

申请号：US16597810

申请日：2019-10-09

Applicant: iCometrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: H03K19/177 ,  H01L27/22 ,  G11C11/16 ,  G11C13/00 ,  H03K19/1776 ,  H03K19/0948 ,  H01L25/18 ,  H01L27/24 ,  G11C11/412 ,  H01L23/538 ,  H01L23/00 ,  G11C11/419 ,  H03K19/20 ,  H03K19/173 ,  H01L45/00 ,  G11C14/00 ,  H03K19/17728 ,  H01L27/11 ,  H01L23/498 ,  H03K19/21

Abstract: A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.