Solar cell stack
    2.
    发明授权

    公开(公告)号:US11296248B2

    公开(公告)日:2022-04-05

    申请号:US14937424

    申请日:2015-11-10

    Abstract: A solar cell stack, having a first semiconductor solar cell having a p-n junction made of a first material with a first lattice constant, and a second semiconductor solar cell having a p-n junction made of a second material with a second lattice constant, and the first lattice constant being at least 0.008 Å smaller than the second lattice constant, and a metamorphic buffer, the metamorphic buffer being formed between the first semiconductor solar cell and the second semiconductor solar cell, and the metamorphic buffer including a series of three layers, and the lattice constant increasing in a series in the direction of the semiconductor solar cell, and the lattice constants of the layers of the metamorphic buffer being bigger than the first lattice constant, two layers of the buffer having a doping, and the difference in the dopant concentration between the two layers being greater than 4E17 cm−3.

    Vertical high-blocking III-V bipolar transistor

    公开(公告)号:US11557665B2

    公开(公告)日:2023-01-17

    申请号:US17368279

    申请日:2021-07-06

    Abstract: A vertical high-blocking III-V bipolar transistor, which includes an emitter, a base and a collector. The emitter has a highly doped emitter semiconductor contact region of a first conductivity type and a first lattice constant. The base has a low-doped base semiconductor region of a second conductivity type and the first lattice constant. The collector has a layered low-doped collector semiconductor region of the first conductivity type with a layer thickness greater than 10 μm and the first lattice constant. The collector has a layered highly doped collector semiconductor contact region of the first conductivity type. A first metallic connecting contact layer is formed in regions being integrally connected to the emitter. A second metallic connecting contact layer is formed in regions being integrally connected to the base. A third metallic connecting contact region is formed at least in regions being arranged beneath the collector.

    Stacked, high-blocking InGaAs semiconductor power diode

    公开(公告)号:US11257909B2

    公开(公告)日:2022-02-22

    申请号:US16863483

    申请日:2020-04-30

    Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

    Stacked high barrier III-V power semiconductor diode

    公开(公告)号:US11245012B2

    公开(公告)日:2022-02-08

    申请号:US16863585

    申请日:2020-04-30

    Abstract: A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.

    Receiver unit
    7.
    发明授权

    公开(公告)号:US10388819B2

    公开(公告)日:2019-08-20

    申请号:US15998506

    申请日:2018-08-16

    Abstract: A receiver unit having an optically operated voltage source, the voltage source including a first stack having an upper side and an underside and being formed on an upper side of a non-Si substrate based on III-V semiconductor layers arranged in the shape of a stack, and having a second electrical terminal contact on the upper side of the first stack and a first electrical terminal contact on an underside of the non-Si substrate, a voltage generated with the aid of the incidence of light onto the upper side of the first stack being present between the two terminal contacts, and including a second stack having a MOS transistor structure having III-V semiconductor layers and including a control terminal and a drain terminal and a source terminal. The MOS transistor structure being designed as a depletion field effect transistor.

    Receiver unit
    10.
    发明申请
    Receiver unit 审中-公开

    公开(公告)号:US20190058074A1

    公开(公告)日:2019-02-21

    申请号:US15998506

    申请日:2018-08-16

    CPC classification number: H01L31/167 H01L27/0629 H01L27/1443 H01L31/0304

    Abstract: A receiver unit having an optically operated voltage source, the voltage source including a first stack having an upper side and an underside and being formed on an upper side of a non-Si substrate based on III-V semiconductor layers arranged in the shape of a stack, and having a second electrical terminal contact on the upper side of the first stack and a first electrical terminal contact on an underside of the non-Si substrate, a voltage generated with the aid of the incidence of light onto the upper side of the first stack being present between the two terminal contacts, and including a second stack having a MOS transistor structure having III-V semiconductor layers and including a control terminal and a drain terminal and a source terminal. The MOS transistor structure being designed as a depletion field effect transistor.

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