Stacked high barrier III-V power semiconductor diode

    公开(公告)号:US11715766B2

    公开(公告)日:2023-08-01

    申请号:US17559656

    申请日:2021-12-22

    CPC classification number: H01L29/157 H01L29/0619 H01L29/205 H01L29/861

    Abstract: A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.

    Receiver unit
    4.
    发明申请
    Receiver unit 审中-公开

    公开(公告)号:US20190058074A1

    公开(公告)日:2019-02-21

    申请号:US15998506

    申请日:2018-08-16

    CPC classification number: H01L31/167 H01L27/0629 H01L27/1443 H01L31/0304

    Abstract: A receiver unit having an optically operated voltage source, the voltage source including a first stack having an upper side and an underside and being formed on an upper side of a non-Si substrate based on III-V semiconductor layers arranged in the shape of a stack, and having a second electrical terminal contact on the upper side of the first stack and a first electrical terminal contact on an underside of the non-Si substrate, a voltage generated with the aid of the incidence of light onto the upper side of the first stack being present between the two terminal contacts, and including a second stack having a MOS transistor structure having III-V semiconductor layers and including a control terminal and a drain terminal and a source terminal. The MOS transistor structure being designed as a depletion field effect transistor.

    Vertical high-blocking III-V bipolar transistor

    公开(公告)号:US11557665B2

    公开(公告)日:2023-01-17

    申请号:US17368279

    申请日:2021-07-06

    Abstract: A vertical high-blocking III-V bipolar transistor, which includes an emitter, a base and a collector. The emitter has a highly doped emitter semiconductor contact region of a first conductivity type and a first lattice constant. The base has a low-doped base semiconductor region of a second conductivity type and the first lattice constant. The collector has a layered low-doped collector semiconductor region of the first conductivity type with a layer thickness greater than 10 μm and the first lattice constant. The collector has a layered highly doped collector semiconductor contact region of the first conductivity type. A first metallic connecting contact layer is formed in regions being integrally connected to the emitter. A second metallic connecting contact layer is formed in regions being integrally connected to the base. A third metallic connecting contact region is formed at least in regions being arranged beneath the collector.

    Stacked, high-blocking InGaAs semiconductor power diode

    公开(公告)号:US11257909B2

    公开(公告)日:2022-02-22

    申请号:US16863483

    申请日:2020-04-30

    Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

    Stacked high barrier III-V power semiconductor diode

    公开(公告)号:US11245012B2

    公开(公告)日:2022-02-08

    申请号:US16863585

    申请日:2020-04-30

    Abstract: A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.

    Receiver unit
    8.
    发明授权

    公开(公告)号:US10388819B2

    公开(公告)日:2019-08-20

    申请号:US15998506

    申请日:2018-08-16

    Abstract: A receiver unit having an optically operated voltage source, the voltage source including a first stack having an upper side and an underside and being formed on an upper side of a non-Si substrate based on III-V semiconductor layers arranged in the shape of a stack, and having a second electrical terminal contact on the upper side of the first stack and a first electrical terminal contact on an underside of the non-Si substrate, a voltage generated with the aid of the incidence of light onto the upper side of the first stack being present between the two terminal contacts, and including a second stack having a MOS transistor structure having III-V semiconductor layers and including a control terminal and a drain terminal and a source terminal. The MOS transistor structure being designed as a depletion field effect transistor.

    Stacked monolithic multijunction solar cell

    公开(公告)号:US11728453B2

    公开(公告)日:2023-08-15

    申请号:US17373199

    申请日:2021-07-12

    CPC classification number: H01L31/0725 H01L31/043 H01L31/074 H01L31/0735

    Abstract: A stacked monolithic multijunction solar cell, which includes a first subcell having a p-n junction with an emitter layer and a base layer, the thickness of the emitter layer being less than the thickness of the base layer at least by a factor of ten, and the first subcell comprising a substrate having a semiconductor material from the groups III and V or a substrate from the group IV, and which further includes a second subcell arranged on the first subcell and a third subcell arranged on the second subcell, the two subcells each including an emitter layer and a base layer, and a tunnel diode and a back side field layer each being formed between the subcells, the thickness of the emitter layer being greater than the thickness of the base layer in each case between the second subcell and in the third subcell.

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