公开(公告)号：US06479257B1

公开(公告)日：2002-11-12

申请号：US09405085

申请日：1999-09-27

申请人： Akira Miyauchi ,  Makoto Ozawa ,  Masato Yoshida ,  Makoto Mizukami

发明人： Akira Miyauchi ,  Makoto Ozawa ,  Masato Yoshida ,  Makoto Mizukami

IPC分类号： C12P2106

CPC分类号： C07K1/1133 ,  C07K1/1136

摘要： The present invention relates to a method for activating protein wherein protein produced in a biologically inactive form (non-natural-form protein) is converted into a biologically active protein (natural-form protein) by bringing it into contact with cultured cells of an organism, and according to the present invention, the non-natural-form protein can be converted efficiently into the natural-form protein having activity, so the yield of the natural-form protein can be further raised by subjecting, e.g., culture of transformant to the activation treatment.

摘要翻译： 本发明涉及一种活化蛋白质的方法，其中以生物活性形式生成的蛋白质（非天然形式蛋白质）通过使其与生物体的培养细胞接触而转化为生物活性蛋白质（天然形式蛋白质） ，根据本发明，可以将非天然形式的蛋白质有效地转化为具有活性的天然形式的蛋白质，因此可以通过使转化体培养成 激活治疗。

公开(公告)号：US09029869B2

公开(公告)日：2015-05-12

申请号：US13034264

申请日：2011-02-24

申请人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

发明人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

IPC分类号： H01L29/15 ,  H01L29/739 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7395 ,  H01L29/1033 ,  H01L29/66333

摘要： One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.

摘要翻译： 半导体器件的一个实施例包括：包含第一和第二主表面的碳化硅衬底; 第一主表面上的第一导电型碳化硅层; 在所述第一碳化硅层的表面处的第二导电型第一碳化硅区域; 在第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 在第一碳化硅区域的表面处的第二导电型第三碳化硅区域; 在第一碳化硅区域和第二碳化硅区域之间形成的杂质浓度高于第一碳化硅区域的第二导电型第四碳化硅区域; 栅极绝缘体; 形成在栅极绝缘体上的栅电极; 层间绝缘体; 连接到所述第二碳化硅区域和所述第三碳化硅区域的第一电极; 和在第二主表面上的第二电极。

公开(公告)号：US08569795B2

公开(公告)日：2013-10-29

申请号：US13217472

申请日：2011-08-25

申请人： Hiroshi Kono ,  Yukio Nakabayashi ,  Takashi Shinohe ,  Makoto Mizukami

发明人： Hiroshi Kono ,  Yukio Nakabayashi ,  Takashi Shinohe ,  Makoto Mizukami

IPC分类号： H01L33/32 ,  H01L29/80 ,  H01L29/16 ,  H01L27/11 ,  H01L27/10

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66068 ,  H01L29/7813

摘要： A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.

摘要翻译： 实施例的半导体器件包括：碳化硅衬底，其包括第一和第二主表面; 设置在碳化硅衬底的第一主表面上的第一导电型第一碳化硅层; 形成在所述第一碳化硅层的表面上的第二导电型第一碳化硅区; 形成在所述第一碳化硅区域的表面上的第一导电型第二碳化硅区域; 形成在所述第一碳化硅区域的表面上的第二导电型第三碳化硅区域; 连续形成在所述第一碳化硅层，所述第一碳化硅区域和所述第二碳化硅区域的表面上的栅极绝缘膜; 形成在所述栅极绝缘膜上的由碳化硅形成的第一电极; 形成在第一电极上的第二电极; 用于覆盖第一和第二电极的层间绝缘膜; 电连接到第二碳化硅区域和第三碳化硅区域的第三电极; 以及形成在碳化硅衬底的第二主表面上的第四电极。

公开(公告)号：US08557695B2

公开(公告)日：2013-10-15

申请号：US12974128

申请日：2010-12-21

申请人： Makoto Mizukami ,  Fumitaka Arai

发明人： Makoto Mizukami ,  Fumitaka Arai

IPC分类号： H01L21/28

CPC分类号： H01L27/11578 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.

摘要翻译： 根据本发明的一个方面，提供一种非易失性半导体存储装置，包括：基板; 堆叠部分，其包括多个导体层和交替堆叠在所述基板上的多个绝缘层，所述多个导体层中的至少一层和所述多个绝缘层形成标记层; 电荷累积膜，其形成在从其顶表面到底表面形成在堆叠部分中的存储器插塞孔的内表面上; 以及通过电荷累积膜形成在存储器插塞孔内部的半导体柱。

公开(公告)号：US07804133B2

公开(公告)日：2010-09-28

申请号：US12022382

申请日：2008-01-30

申请人： Takeshi Murata ,  Makoto Mizukami ,  Fumitaka Arai

发明人： Takeshi Murata ,  Makoto Mizukami ,  Fumitaka Arai

IPC分类号： H01L27/115

CPC分类号： H01L27/105 ,  H01L21/84 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/1203

摘要： Semiconductor storage devices in which a plurality of semiconductor element devices having different functions are disposed in the appropriate region of the partial SOI substrate and the interface between each gate insulator and each gate electrode is formed to be the same level, and manufacturing methods thereof are disclosed. According to one aspect, there is provided a semiconductor storage device includes a first semiconductor region provided in a semiconductor substrate including a buried insulator having opening portions, a second semiconductor region without including buried insulator, a plurality of first semiconductor element devices disposed above the buried insulator, a plurality of second semiconductor element devices each disposed in a region including a region above the opening portion of the buried insulator, and a plurality of third semiconductor element devices disposed in the second semiconductor region.

摘要翻译： 其中具有不同功能的多个半导体元件器件设置在部分SOI衬底的适当区域中并且每个栅绝缘体和每个栅电极之间的界面形成为相同水平的半导体存储器件，并且其制造方法被公开 。 根据一个方面，提供一种半导体存储装置，包括设置在包括具有开口部分的埋入式绝缘体的半导体衬底中的第一半导体区域，不包括埋入绝缘体的第二半导体区域，设置在掩埋层上方的多个第一半导体元件器件 绝缘体，多个第二半导体元件器件，每个第二半导体元件器件设置在包括所述埋入绝缘体的开口部分上方的区域的区域中，以及设置在所述第二半导体区域中的多个第三半导体元件器件。

公开(公告)号：US07696559B2

公开(公告)日：2010-04-13

申请号：US11616522

申请日：2006-12-27

申请人： Fumitaka Arai ,  Riichiro Shirota ,  Makoto Mizukami

发明人： Fumitaka Arai ,  Riichiro Shirota ,  Makoto Mizukami

IPC分类号： H01L27/115

CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained, pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

摘要翻译： 半导体存储器件包括：在单元阵列区域中形成有杂质扩散层的半导体衬底; 形成在电池阵列区域上的栅极布线堆叠体，其中多个栅极布线彼此堆叠并且用绝缘膜分离; 形成在栅极布线堆叠体的侧表面上的栅极绝缘膜，其中包含绝缘电荷存储层，沿着栅极布线堆叠体布置的柱状半导体层，其一个侧表面与栅极布线相对 堆叠体经由栅极绝缘膜，每个柱状半导体层具有与杂质扩散层相同的导电类型; 以及形成为与柱状半导体层的上表面接触并与栅极布线相交的数据线。

公开(公告)号：US20080253183A1

公开(公告)日：2008-10-16

申请号：US12061075

申请日：2008-04-02

申请人： Makoto Mizukami ,  Kiyohito Nishihara

发明人： Makoto Mizukami ,  Kiyohito Nishihara

IPC分类号： G11C16/04

CPC分类号： H01L27/105 ,  H01L27/0688 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556

摘要： A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction. The second interconnection layers extend upward and are separated from each other by insulating films.

摘要翻译： 半导体存储器件包括具有包括第一上表面和高于第一上表面的第二上表面的步骤的衬底，形成在第一上表面上的存储单元阵列和形成在第二上表面上的外围电路， 以向存储单元阵列提供电信号。 存储单元阵列包括具有分别连接到第一互连层的多个第一互连层和多个第二互连层的层叠结构。 第一互连层堆叠在第一上表面上，通过绝缘膜彼此分离，并沿第一方向延伸。 第二互连层向上延伸并且通过绝缘膜彼此分离。

公开(公告)号：US07368783B2

公开(公告)日：2008-05-06

申请号：US11230492

申请日：2005-09-21

申请人： Makoto Mizukami ,  Takashi Shinohe

发明人： Makoto Mizukami ,  Takashi Shinohe

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底，形成在衬底的第一主表面上的第一导电类型的轻掺杂半导体层，形成在岛状区域上的第一导电类型的第一半导体区域 在所述轻掺杂半导体层上，包围所述第一半导体区并且埋藏在比所述第一半导体区更深的位置的第一电极，形成在所述衬底的所述第二主表面上的第二半导体区， 在第一电极的底表面和第二半导体区域之间的轻掺杂半导体层，包括第一导电类型的第一场弛豫层和形成在第一场弛豫层两端的第二导电类型的第二场弛豫层 ，形成在第一和第二半导体区域上的第二和第三电极， 分别。

公开(公告)号：US5936794A

公开(公告)日：1999-08-10

申请号：US543996

申请日：1995-10-17

申请人： Makoto Mizukami ,  Nobuyoshi Izawa ,  Kikuji Katoh ,  Yoshihiro Isomura ,  Yoshihiro Sako

发明人： Makoto Mizukami ,  Nobuyoshi Izawa ,  Kikuji Katoh ,  Yoshihiro Isomura ,  Yoshihiro Sako

IPC分类号： G06F3/06 ,  G11B17/22 ,  G11B27/00 ,  G11B15/68

CPC分类号： G11B17/225 ,  G11B27/002 ,  G11B17/228 ,  G11B2220/20 ,  G11B2220/41

摘要： A media library system capable of carrying out an access to each recording medium in very short time. A media exchange operation is controlled such that the storage cells of the storehouse are divided into at least two groups arranged in an order of average distances with respect to the media drive, including a first group with a shortest average distance with respect to the media drive, and when the previously used recording medium was mounted on the media drive from the first group, the previously used recording medium is stored in the first group, whereas when the previously used recording medium was mounted on the media drive from one group other than the first group, one recording medium with a lowest utilization frequency among an adjacent group of that one group having a shorter average distance with respect to the media drive than that one group is moved from that adjacent group to that one group and then the previously used recording medium is stored in that adjacent group.

摘要翻译： 一种媒体库系统，能够在非常短的时间内对每个记录介质进行访问。 控制媒体交换操作，使得仓库的存储单元被划分为相对于介质驱动器以平均距离的顺序排列的至少两个组，包括相对于介质驱动器具有最短平均距离的第一组 ，并且当先前使用的记录介质从第一组安装在介质驱动器上时，先前使用的记录介质被存储在第一组中，而当先前使用的记录介质从除了 第一组，具有相对于介质驱动器的平均距离较短的该组的相邻组中具有最低利用频率的一个记录介质，而不是一组从该相邻组移动到该组，然后是先前使用的记录 介质存储在该相邻组中。

公开(公告)号：US5242728A

公开(公告)日：1993-09-07

申请号：US618252

申请日：1990-11-21

申请人： Makoto Mizukami

发明人： Makoto Mizukami

IPC分类号： G11B5/64 ,  G11B5/66 ,  G11B5/73 ,  G11B5/738

CPC分类号： G11B5/7325 ,  G11B5/656 ,  Y10S428/90 ,  Y10T428/12861

摘要： A magnetic recording medium includes a primary coat formed on a non-magnetic base and a magnetic film of a CoP alloy formed on the primary coat, wherein the primary coat is a metal simple substance selected from the group of Cr, V and W or an alloy of two or more of them, and the magnetic film is at least one of the CoP alloys represented by the following formulae, wherein X, Y, Z, a and b denote atomic percent (at %):Co.sub.X P.sub.Y Pt.sub.Zwhere Y and Z denote 4.ltoreq.Y.ltoreq.11, and 2.ltoreq.Z.ltoreq.10, respectively, with the balance being X;Co.sub.X P.sub.Y Pt.sub.Z Ni.sub.awhere Y, Z and a denote 5.ltoreq.Y.ltoreq.9, 2.ltoreq.Z.ltoreq.10 and 5.ltoreq.a.ltoreq.35, respectively, with the balance being X; andCo.sub.X P.sub.Y Pt.sub.Z Ni.sub.a Cr.sub.bwhere Y, Z and a and b denote 5.ltoreq.Y.ltoreq.9, 2.ltoreq.Z.ltoreq.10, 5.ltoreq.a.ltoreq.35 and 0

摘要翻译： 磁记录介质包括在非磁性基底上形成的初级涂层和在初级涂层上形成的CoP合金的磁性膜，其中初级涂层是选自Cr，V和W的金属单体，或 其中X，Y，Z，a和b表示原子百分数（at％）：CoXPYPtZ，其中Y和Z表示 4