公开(公告)号：US08399936B2

公开(公告)日：2013-03-19

申请号：US12790220

申请日：2010-05-28

申请人： Albert Birner ,  Uwe Hoeckele ,  Thomas Kunstmann ,  Uwe Seidel

发明人： Albert Birner ,  Uwe Hoeckele ,  Thomas Kunstmann ,  Uwe Seidel

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming a through substrate via by partially filling an opening with a fill material, and forming a first insulating layer over the first fill material thereby forming a gap over the opening. The method further includes forming a second insulating layer to close the gap thereby forming an enclosed cavity within the opening.

摘要翻译： 描述了在形成半导体部件时通过衬底通孔形成的结构和方法。 在一个实施例中，本发明描述了一种通过用填充材料部分地填充开口形成贯通衬底通孔的方法，并且在第一填充材料之上形成第一绝缘层，从而在开口上形成间隙。 该方法还包括形成第二绝缘层以封闭间隙，从而在开口内形成封闭空腔。

公开(公告)号：US20090302480A1

公开(公告)日：2009-12-10

申请号：US12135059

申请日：2008-06-06

申请人： Albert Birner ,  Uwe Hoeckele ,  Thomas Kunstmann ,  Uwe Seidel

发明人： Albert Birner ,  Uwe Hoeckele ,  Thomas Kunstmann ,  Uwe Seidel

IPC分类号： H01L23/48 ,  H01L21/31

CPC分类号： H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming a through substrate via by partially filling an opening with a fill material, and forming a first insulating layer over the first fill material thereby forming a gap over the opening. The method further includes forming a second insulating layer to close the gap thereby forming an enclosed cavity within the opening.

摘要翻译： 描述了在形成半导体部件时通过衬底通孔形成的结构和方法。 在一个实施例中，本发明描述了一种通过用填充材料部分地填充开口形成贯通衬底通孔的方法，并且在第一填充材料之上形成第一绝缘层，从而在开口上形成间隙。 该方法还包括形成第二绝缘层以封闭间隙，从而在开口内形成封闭空腔。

公开(公告)号：US07772123B2

公开(公告)日：2010-08-10

申请号：US12135059

申请日：2008-06-06

申请人： Albert Birner ,  Uwe Hoeckele ,  Thomas Kunstmann ,  Uwe Seidel

发明人： Albert Birner ,  Uwe Hoeckele ,  Thomas Kunstmann ,  Uwe Seidel

IPC分类号： H01L21/311

CPC分类号： H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.

摘要翻译： 描述了在形成半导体部件时通过衬底通孔形成的结构和方法。 在一个实施例中，本发明描述了一种通过用第一填充材料填充开口形成通孔基底通孔的方法，并且在第一填充材料上沉积第一绝缘层，第一绝缘层未沉积在填充材料的侧壁上 所述开口，其中所述第一绝缘层的侧壁在所述开口上形成间隙。 该方法还包括通过使用第二绝缘层密封开口来形成空隙。

公开(公告)号：US20100230818A1

公开(公告)日：2010-09-16

申请号：US12790220

申请日：2010-05-28

申请人： Albert Birner ,  Uwe Hoeckele ,  Thomas Kunstmann ,  Uwe Seidel

发明人： Albert Birner ,  Uwe Hoeckele ,  Thomas Kunstmann ,  Uwe Seidel

IPC分类号： H01L23/48

CPC分类号： H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming a through substrate via by partially filling an opening with a fill material, and forming a first insulating layer over the first fill material thereby forming a gap over the opening. The method further includes forming a second insulating layer to close the gap thereby forming an enclosed cavity within the opening.

摘要翻译： 描述了在形成半导体部件时通过衬底通孔形成的结构和方法。 在一个实施例中，本发明描述了一种通过用填充材料部分地填充开口形成贯通衬底通孔的方法，并且在第一填充材料之上形成第一绝缘层，从而在开口上形成间隙。 该方法还包括形成第二绝缘层以封闭间隙，从而在开口内形成封闭空腔。

公开(公告)号：US08598593B2

公开(公告)日：2013-12-03

申请号：US13184346

申请日：2011-07-15

申请人： Uwe Hoeckele

发明人： Uwe Hoeckele

IPC分类号： H01L29/15 ,  H01L29/40

CPC分类号： H01L21/76886 ,  H01L21/0237 ,  H01L21/02444 ,  H01L21/02527 ,  H01L21/02675 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76867 ,  H01L23/53276 ,  H01L45/149 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/81 ,  H01L2924/00

摘要： A chip includes an integrated circuit and a carbonic layer. The carbonic layer includes a graphite-like carbon, wherein a lateral conducting path through the graphite-like carbon electrically connects two circuit elements of the integrated circuit.

摘要翻译： 芯片包括集成电路和碳层。 碳层包括石墨状碳，其中通过石墨状碳的横向导电路径电连接集成电路的两个电路元件。

公开(公告)号：US09236290B2

公开(公告)日：2016-01-12

申请号：US13365774

申请日：2012-02-03

申请人： Carsten Ahrens ,  Rudolf Berger ,  Manfred Frank ,  Uwe Hoeckele ,  Bernhard Knott ,  Ulrich Krumbein ,  Wolfgang Lehnert ,  Berthold Schuderer ,  Juergen Wagner ,  Stefan Willkofer

发明人： Carsten Ahrens ,  Rudolf Berger ,  Manfred Frank ,  Uwe Hoeckele ,  Bernhard Knott ,  Ulrich Krumbein ,  Wolfgang Lehnert ,  Berthold Schuderer ,  Juergen Wagner ,  Stefan Willkofer

IPC分类号： H01L21/762 ,  H01L23/31 ,  H01L21/78 ,  H01L23/48

CPC分类号： H01L21/76224 ,  H01L21/762 ,  H01L21/76232 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3185 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench.

摘要翻译： 一种制造具有侧壁绝缘体的半导体器件的方法包括提供具有第一侧和与第一侧相对的第二侧的半导体本体。 至少一个第一沟槽至少部分地填充有绝缘材料，该绝缘材料从朝向第二侧的方向的第一侧进入半导体本体。 在第一半导体器件的第一半导体体区域和第二半导体器件的第二半导体本体区域之间产生至少一个第一沟槽。 隔离沟槽从半导体本体的第一侧沿第一和第二半导体主体区域之间的半导体本体的第二侧的方向延伸，使得第一沟槽的绝缘材料的至少一部分至少与第一沟槽的绝缘材料相邻 隔离沟槽的侧壁。 半导体主体的第二面部分地被去除到隔离沟槽的一侧。

公开(公告)号：US07834427B2

公开(公告)日：2010-11-16

申请号：US11680320

申请日：2007-02-28

申请人： Thomas Detzel ,  Hubert Maier ,  Kai-Alexander Schreiber ,  Stefan Woehlert ,  Uwe Hoeckele

发明人： Thomas Detzel ,  Hubert Maier ,  Kai-Alexander Schreiber ,  Stefan Woehlert ,  Uwe Hoeckele

IPC分类号： H01L29/78 ,  H01L23/52

CPC分类号： H01L21/76832 ,  H01L21/76829 ,  H01L21/76837 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/41741 ,  H01L29/7803 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least one cutout, an insulating filling layer, formed on the first interconnect layer and the carrier substrate and fills at least one cutout, an SiON layer, formed on the filling layer, and a second interconnect layer, formed over the SiON layer.

摘要翻译： 公开了一种包括半导体装置，功率半导体元件和相关制造方法的集成电路。 一个实施例包括形成在载体基板上并具有至少一个切口的绝缘填充层的载体基板，第一互连层，形成在第一互连层和载体基板上并填充至少一个切口，SiON层， 形成在所述填充层上，以及形成在所述SiON层上的第二互连层。

公开(公告)号：US08597531B2

公开(公告)日：2013-12-03

申请号：US12417100

申请日：2009-04-02

申请人： Sandra Obernhuber ,  Christof Jalics ,  Joerg Adler ,  Uwe Hoeckele ,  Walter Preis ,  Reinhard Goellner ,  Tanja Schest ,  Patricia Nickut

发明人： Sandra Obernhuber ,  Christof Jalics ,  Joerg Adler ,  Uwe Hoeckele ,  Walter Preis ,  Reinhard Goellner ,  Tanja Schest ,  Patricia Nickut

IPC分类号： C03C15/00

CPC分类号： H01L41/297 ,  H03H3/04

摘要： A method for manufacturing a device on a substrate includes forming a layer structure on the substrate, forming an auxiliary layer on the layer structure, forming a planarization layer on the auxiliary layer and on the substrate, exposing the auxiliary layer by a chemical mechanical polishing process and removing at least partly the auxiliary layer to form a planar surface of the remaining auxiliary layer or of the layer structure and the planarization layer. The chemical mechanical polishing process has a first removal rate with respect to the planarization layer and a second removal rate with respect to the auxiliary layer and the first removal rate is greater than the second removal rate.

公开(公告)号：US20130256857A1

公开(公告)日：2013-10-03

申请号：US13431251

申请日：2012-03-27

申请人： Hermann Gruber ,  Joachim Mahler ,  Uwe Hoeckele ,  Anton Prueckl ,  Thomas Fischer ,  Matthias Schmidt

发明人： Hermann Gruber ,  Joachim Mahler ,  Uwe Hoeckele ,  Anton Prueckl ,  Thomas Fischer ,  Matthias Schmidt

IPC分类号： H01L25/07 ,  H01L23/495 ,  H01L21/50 ,  H01L23/28

CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L23/291 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/85203 ,  H01L2224/85207 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01047 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： In one embodiment, a method of forming a semiconductor package comprises providing a first die having contact regions on a top surface but not on an opposite bottom surface. A dielectric liner layer is deposited under the bottom surface of the first die. The first die is attached with the deposited dielectric liner layer to a die paddle of a substrate.

摘要翻译： 在一个实施例中，形成半导体封装的方法包括提供在顶表面上但不在相对的底表面上具有接触区域的第一裸片。 介电衬垫层沉积在第一管芯的底表面下方。 第一裸片与沉积的介电衬垫层连接到衬底的裸片上。

公开(公告)号：US20130015583A1

公开(公告)日：2013-01-17

申请号：US13184346

申请日：2011-07-15

申请人： Uwe Hoeckele

发明人： Uwe Hoeckele

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76886 ,  H01L21/0237 ,  H01L21/02444 ,  H01L21/02527 ,  H01L21/02675 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76867 ,  H01L23/53276 ,  H01L45/149 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/81 ,  H01L2924/00

摘要： A chip includes an integrated circuit and a carbonic layer. The carbonic layer includes a graphite-like carbon, wherein a lateral conducting path through the graphite-like carbon electrically connects two circuit elements of the integrated circuit.