公开(公告)号：US06713360B2

公开(公告)日：2004-03-30

申请号：US10218027

申请日：2002-08-12

申请人： Amitabh Jain ,  Kaiping Liu ,  Zhiqiang Wu

发明人： Amitabh Jain ,  Kaiping Liu ,  Zhiqiang Wu

IPC分类号： H01L21331

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/2652 ,  H01L29/1083

摘要： The present invention provides a method for forming a transistor junction in a semiconductor wafer by implanting a dopant material (116) into the semiconductor wafer, implanting a halo material (110) into the semiconductor wafer (102), selecting a fluorine dose and energy to tailor one or more characteristics of the transistor, implanting fluorine into the semiconductor wafer at the selected dose and energy, activating the dopant material using a thermal process and annealing the semiconductor wafer to remove residual fluorine. The one or more characteristics of the transistor may include halo segregation, halo diffusion, the sharpness of the halo profile, dopant activation, dopant profile sharpness, drive current, bottom wall capacitance or near edge capacitance.

摘要翻译： 本发明提供了一种通过将掺杂剂材料（116）注入到半导体晶片中而在半导体晶片中形成晶体管结的方法，将卤素材料（110）注入到半导体晶片（102）中，选择氟剂量和能量 定制晶体管的一个或多个特性，以选择的剂量和能量将氟注入到半导体晶片中，使用热处理激活掺杂剂材料并退火半导体晶片以除去残留的氟。 晶体管的一个或多个特性可以包括卤素偏析，卤素扩散，晕轮廓的锐度，掺杂剂激活，掺杂剂分布锐度，驱动电流，底壁电容或近边缘电容。

公开(公告)号：US20060163651A1

公开(公告)日：2006-07-27

申请号：US11042415

申请日：2005-01-25

申请人： Antonio Rotondaro ,  Kaiping Liu ,  Jihong Chen ,  Amitabh Jain

发明人： Antonio Rotondaro ,  Kaiping Liu ,  Jihong Chen ,  Amitabh Jain

IPC分类号： H01L29/06

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/823814 ,  H01L21/823871

摘要： The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.

摘要翻译： 本发明提供了晶体管器件的制造方法，集成电路的制造方法以及晶体管器件。 制造晶体管器件的方法以及其它步骤包括在衬底上形成栅极结构，并在栅极结构附近形成衬底中的源极/漏极区域，源极/漏极区域具有与衬底形成电连接的边界 。 该方法还包括在衬底中形成位错环，位错环不延伸到源/漏区的边界之外。

公开(公告)号：US07691714B2

公开(公告)日：2010-04-06

申请号：US11042415

申请日：2005-01-25

申请人： Antonio Luis Pacheco Rotondaro ,  Kaiping Liu ,  Jihong Chen ,  Amitabh Jain

发明人： Antonio Luis Pacheco Rotondaro ,  Kaiping Liu ,  Jihong Chen ,  Amitabh Jain

IPC分类号： H01L21/336 ,  H01L21/337

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/823814 ,  H01L21/823871

摘要： The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.

摘要翻译： 本发明提供了晶体管器件的制造方法，集成电路的制造方法以及晶体管器件。 制造晶体管器件的方法以及其他步骤包括在衬底上形成栅极结构，并在栅极结构附近形成衬底中的源极/漏极区域，源极/漏极区域具有与衬底形成电连接的边界 。 该方法还包括在衬底中形成位错环，位错环不延伸到源/漏区的边界之外。

公开(公告)号：US08580663B2

公开(公告)日：2013-11-12

申请号：US13217577

申请日：2011-08-25

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/426

CPC分类号： H01L21/823814 ,  H01L21/2251 ,  H01L21/2255 ,  H01L21/26566 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/84 ,  H01L29/6659 ,  H01L29/7833

摘要： A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm−2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the IC substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both NLDD and PLDD regions.

摘要翻译： 公开了一种用于在IC衬底，特别是MOS晶体管中的LDD区域形成平均掺杂剂量高于1014cm -2的深度小于20nm的扩散区域的工艺。 使用气体簇离子束（GCIB）注入，分子离子注入或原子离子注入将掺杂剂注入到源电介质层中，导致IC衬底中的可忽略的损伤。 尖峰退火或激光退火将注入的掺杂剂扩散到IC衬底中。 本发明的方法也可以应用于形成源极和漏极（S / D）区域。 一个源介质层可用于形成NLDD和PLDD区域。

公开(公告)号：US08252609B2

公开(公告)日：2012-08-28

申请号：US12757704

申请日：2010-04-09

申请人： Brian K. Kirkpatrick ,  Steven L. Prins ,  Amitabh Jain

发明人： Brian K. Kirkpatrick ,  Steven L. Prins ,  Amitabh Jain

IPC分类号： H01L21/26 ,  H01L21/66

CPC分类号： H01L21/26506 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02667 ,  H01L22/12 ,  H01L22/20

摘要： A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ≦5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization.

摘要翻译： 一种用于减小具有半导体表面的晶片的曲率的方法。 识别一个或多个工艺步骤，在该处理步骤中，晶片呈现最大的曲率，和/或晶片曲率，其可以降低模具的产量。 晶体损伤过程将半导体表面的至少一部分转化成至少一个非晶表面区域在晶体损坏之后或同时与晶体有害的同时，非晶表面区域通过重结晶退火重结晶，使晶片退火一段时间， 足以使非晶表面区域再结晶的温度。 由于再结晶提供的平均晶片曲率的减小，随后的光刻步骤变得容易。

公开(公告)号：US07883573B2

公开(公告)日：2011-02-08

申请号：US11697790

申请日：2007-04-09

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： C09D201/00

CPC分类号： H01J37/08 ,  H01J2237/31701 ,  H01L21/26513 ,  H01L21/823418 ,  H01L29/6659 ,  Y10S252/95

摘要： The present invention provides, for use in a semiconductor manufacturing process, a method (100) of preparing an ion-implantation source material. The method includes providing (110) a deliquescent ion implantation source material and mixing (110) the deliquescent ion implantation source material with an organic liquid to form a paste.

摘要翻译： 为了在半导体制造工艺中使用本发明，提供了制备离子注入源材料的方法（100）。 该方法包括提供（110）潮解离子注入源材料，并将潮解离子注入源材料与有机液体混合（110）以形成糊状物。

公开(公告)号：US07678637B2

公开(公告)日：2010-03-16

申请号：US12209270

申请日：2008-09-12

申请人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

发明人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1087 ,  H01L29/7847

摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

摘要翻译： 对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。 本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。 实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。 来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

公开(公告)号：US07670917B2

公开(公告)日：2010-03-02

申请号：US11853328

申请日：2007-09-11

申请人： Amitabh Jain ,  Manoj Mehrotra

发明人： Amitabh Jain ,  Manoj Mehrotra

IPC分类号： H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28044 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845

摘要： In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal.

摘要翻译： 在一个方面，提供一种制造半导体器件的方法，包括在半导体衬底上形成栅电极，在栅电极附近形成源极/漏极，在栅电极上沉积应力诱导层。 在至少约1100℃的温度下沉积应力诱导层至少约300微秒的时间之后，至少在栅电极上进行激光退火，并且半导体器件经受热 在进行激光退火之后退火。

公开(公告)号：US20070293012A1

公开(公告)日：2007-12-20

申请号：US11762905

申请日：2007-06-14

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/336

CPC分类号： H01L21/324 ,  H01L21/268 ,  H01L29/6659 ,  H01L29/7833

摘要： Exemplary embodiments provide methods for reducing and/or removing slip and plastic deformations in semiconductor materials by use of one or more ultra-fast thermal spike anneals. The ultra-fast thermal spike anneal can be an ultra-high temperature (UHT) anneal having an ultra-short annealing time. During the ultra-fast thermal spike anneal, an increased annealing power density can be used to achieve a desired annealing temperature required by manufacturing processes. In an exemplary embodiment, the annealing temperature can be in the range of about 1150° C. to about 1390° C. and the annealing dwell time can be on the order of less than about 0.8 milliseconds. In various embodiments, the disclosed spike-annealing processes can be used to fabrication structures and regions of MOS transistor devices, for example, drain and source extension regions and/or drain and source regions.

摘要翻译： 示例性实施例提供了通过使用一个或多个超快速热穗退火来减少和/或去除半导体材料中的滑移和塑性变形的方法。 超快速热尖峰退火可以是具有超短退火时间的超高温（UHT）退火。 在超快速热穗退火期间，可以使用增加的退火功率密度来实现制造工艺所需的期望的退火温度。 在示例性实施例中，退火温度可以在约1150℃至约1390℃的范围内，并且退火停留时间可以在小于约0.8毫秒的数量级。 在各种实施例中，所公开的尖峰退火工艺可用于制造MOS晶体管器件的结构和区域，例如漏极和源极延伸区域和/或漏极和源极区域。

公开(公告)号：US07306995B2

公开(公告)日：2007-12-11

申请号：US10739973

申请日：2003-12-17

申请人： Haowen Bu ,  Clinton L. Montgomery ,  Amitabh Jain

发明人： Haowen Bu ,  Clinton L. Montgomery ,  Amitabh Jain

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/3145 ,  H01L21/31612 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.