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    Integrated circuit fuse with localized fusing point
    3.
    发明授权
    Integrated circuit fuse with localized fusing point 有权
    具有局部熔断点的集成电路保险丝

    公开(公告)号：US06271574B1

    公开(公告)日：2001-08-07

    申请号：US09310264

    申请日：1999-05-12

    申请人： Philippe Delpech ,  Nathalie Revil

    发明人： Philippe Delpech ,  Nathalie Revil

    IPC分类号： H01L2900

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit fuse includes a substantially bar-shaped central region and zones having electrical contacts. The central region includes a thinned zone forming a weak point facilitating fusing of the fuse by increasing the local current density as compared to standard fusing conditions. The thinned zone is preferably obtained by proximity optical effect between the fuse and adjacent dummy elements.

    摘要翻译： 集成电路熔断器包括大致条形中心区域和具有电触点的区域。 中心区域包括形成弱点的薄区，与标准熔化条件相比，通过增加局部电流密度便于保险丝的熔合。 优选通过熔丝和相邻虚设元件之间的接近光学效应来获得变薄区。

    Method for fabricating an integrated circuit comprising a three-dimensional capacitor
    4.
    发明授权
    Method for fabricating an integrated circuit comprising a three-dimensional capacitor 有权
    一种制造包括三维电容器的集成电路的方法

    公开(公告)号：US07479424B2

    公开(公告)日：2009-01-20

    申请号：US11405680

    申请日：2006-04-17

    申请人： Jean-Christophe Giraudin ,  Sébastien Cremer ,  Philippe Delpech

    发明人： Jean-Christophe Giraudin ,  Sébastien Cremer ,  Philippe Delpech

    IPC分类号： H01L21/8242 ,  H01L29/76

    CPC分类号： H01L28/91 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L28/40 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A capacitor fabricated, within an integrated circuit, has at least two capacitive trenches extending within a dielectric material. A metal layer is produced which is embedded in the dielectric material. To form the capacitor, the dielectric material is etched, with etching stopped at the metal layer so as to form the trenches. A layer of conductive material forming the lower electrode of the capacitor is then deposited at least on the sidewalls of the trenches and in contact with the metal layer. A dielectric layer is then deposited within the trenches. A layer of conductive material forming the upper electrode of the capacitor is then deposited within the trenches.

    摘要翻译： 在集成电路内制造的电容器具有在电介质材料内延伸的至少两个电容沟槽。 制造嵌入电介质材料的金属层。 为了形成电容器，蚀刻介电材料，在金属层处停止蚀刻，形成沟槽。 形成电容器的下电极的导电材料层然后至少沉积在沟槽的侧壁上并与金属层接触。 然后在沟槽内沉积介电层。 形成电容器的上电极的导电材料层然后沉积在沟槽内。

    Integrated circuit fuse, with focusing of current
    6.
    发明授权
    Integrated circuit fuse, with focusing of current 有权
    集成电路保险丝，具有电流聚焦

    公开(公告)号：US06469363B1

    公开(公告)日：2002-10-22

    申请号：US09304919

    申请日：1999-05-04

    申请人： Philippe Delpech ,  Nathalie Revil

    发明人： Philippe Delpech ,  Nathalie Revil

    IPC分类号： H01L2900

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit fuse is formed on a substrate by etching a polysilicon, metal or alloy layer deposited thereon to include a central region, at the end of which are zones with electrical contacts. The central region has at least two first electrically parallel arms. A zone of intersection of the first two arms forms a point for focusing a fusing current which facilitates the fusing of the fuse by increasing local current density flowing through the integrated circuit.

    摘要翻译： 通过蚀刻沉积在其上的多晶硅，金属或合金层以包括中心区域在基板上形成集成电路保险丝，其中末端是具有电触点的区域。 中心区域具有至少两个第一电平行臂。 前两个臂的相交区域形成用于聚焦定影电流的点，其通过增加流过集成电路的局部电流密度来促进熔丝的熔合。

    Integrated circuit comprising at least one capacitor and process for forming the capacitor
    8.
    发明授权
    Integrated circuit comprising at least one capacitor and process for forming the capacitor 有权
    集成电路包括至少一个电容器和用于形成电容器的工艺

    公开(公告)号：US07667292B2

    公开(公告)日：2010-02-23

    申请号：US11415393

    申请日：2006-05-01

    申请人： Jean-Christophe Giraudin ,  Vincent Fiori ,  Philippe Delpech

    发明人： Jean-Christophe Giraudin ,  Vincent Fiori ,  Philippe Delpech

    IPC分类号： H01L27/08

    CPC分类号： H01L29/66181 ,  H01L21/31612 ,  H01L21/31633 ,  H01L27/0805 ,  H01L28/91

    摘要： An integrated circuit includes at least one capacitor that is formed on a layer provided with at least one first trench. The capacitor, which is provided with a dielectric layer that separates two electrodes, conforms to the shape of the first trench, but leaves a part of the first trench unfilled. A material capable of absorbing stresses associated with the displacements of the walls of the trench is placed in the trench to fill the part of the first trench. A second trench is formed at least partly surrounding the first trench. This second trench is also at least partly filled with a material capable of absorbing stresses associated with the displacements of the walls of the second trench. A void may be included in the stress absorbing material which fills either of the first or second trenches.

    摘要翻译： 集成电路包括至少一个形成在设置有至少一个第一沟槽的层上的电容器。 设置有分隔两个电极的电介质层的电容器符合第一沟槽的形状，但是留下未填充的第一沟槽的一部分。 能够吸收与沟槽的壁的位移相关联的应力的材料被放置在沟槽中以填充第一沟槽的一部分。 至少部分地围绕第一沟槽形成第二沟槽。 该第二沟槽还至少部分地填充有能够吸收与第二沟槽的壁的位移相关联的应力的材料。 在应力吸收材料中可以包含空隙，填充第一或第二沟槽中的任一个。

    Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit
    9.
    发明授权
    Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit 有权
    通过在集成电路的互连电介质层中使用金属沉积物来制造电容器的方法

    公开(公告)号：US07563687B2

    公开(公告)日：2009-07-21

    申请号：US11302971

    申请日：2005-12-14

    申请人： Jean-Christophe Giraudin ,  Sébastien Cremer ,  Philippe Delpech

    发明人： Jean-Christophe Giraudin ,  Sébastien Cremer ,  Philippe Delpech

    IPC分类号： H01L21/20

    CPC分类号： H01L21/32139 ,  H01L21/84 ,  H01L23/5223 ,  H01L27/13 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (21); Deposit of a first insulator layer (31) on the first metallic layer (21); Deposit of a second metallic layer (41) on the first insulator layer (31); Formation of an upper electrode (4) in the second layer metallic (41); Deposit of a second insulator layer (13) covering the upper electrode (4); Etching of the second insulator layer to form a spacer (14) on this first insulator layer surrounding the upper electrode (4); then Formation of a lower electrode (2) and a dielectric (3) by removal of parts from the first metallic layer and insulator not covered by the upper electrode (4) or the spacer (14); and Formation of an interconnection line (5). This process allows for manufacturing capacitors with an increased performance, in a simplified fashion at lower cost and with an auto-alignment.

    摘要翻译： 互连层中的电容器的制造方法包括以下阶段：第一金属层（21）的沉积; 在第一金属层（21）上沉积第一绝缘体层（31）; 在第一绝缘体层（31）上沉积第二金属层（41）; 在第二层金属（41）中形成上电极（4）; 沉积覆盖上电极（4）的第二绝缘体层（13）。 蚀刻第二绝缘体层以在围绕上电极（4）的该第一绝缘体层上形成间隔物（14）; 然后通过从第一金属层和未被上电极（4）或间隔物（14）覆盖的绝缘体去除零件来形成下电极（2）和电介质（3）; 和互连线（5）的形成。 该过程允许以更低的成本和自动对准以简化的方式制造具有增加的性能的电容器。

    CREATION OF CAPACITORS EQUIPPED WITH MEANS TO REDUCE THE STRESSES IN THE METAL MATERIAL OF THEIR LOWER STRUCTURES
    10.
    发明申请
    CREATION OF CAPACITORS EQUIPPED WITH MEANS TO REDUCE THE STRESSES IN THE METAL MATERIAL OF THEIR LOWER STRUCTURES 有权
    具有减少其结构的金属材料应力的手段的电容器的创建

    公开(公告)号：US20090040684A1

    公开(公告)日：2009-02-12

    申请号：US12134490

    申请日：2008-06-06

    申请人： Sebastien Cremer ,  Philippe Delpech ,  Sylvie Bruyere

    发明人： Sebastien Cremer ,  Philippe Delpech ,  Sylvie Bruyere

    IPC分类号： H01G4/30 ,  H01G9/00

    CPC分类号： H01L28/87 ,  H01L28/91 ,  Y10T29/417

    摘要： The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.

    摘要翻译： 用于形成具有至少一个二维或三维电容器的微电子器件的方法包括在衬底上产生多个部件和多个叠加的金属互连电平。 在金属互连层上形成绝缘层，在其中形成有一个或多个由该绝缘层形成的绝缘块的下一个金属互连层的水平金属区。 该区域被设计成形成电容器的下部结构部分。