公开(公告)号：US5817405A

公开(公告)日：1998-10-06

申请号：US795180

申请日：1997-02-04

申请人： Anikumar Chinuprasad Bhatt ,  Ashwinkumar Chinuprasad Bhatt ,  Robert Jeffrey Day ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight ,  Richard William Malek ,  Voya Rista Markovich

发明人： Anikumar Chinuprasad Bhatt ,  Ashwinkumar Chinuprasad Bhatt ,  Robert Jeffrey Day ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight ,  Richard William Malek ,  Voya Rista Markovich

IPC分类号： H05K1/02 ,  H05K3/06 ,  H05K3/10 ,  H05K3/42 ,  B32B9/00

CPC分类号： H05K1/0265 ,  H05K3/108 ,  H05K3/428 ,  H05K1/0263 ,  H05K2201/0347 ,  H05K2201/09727 ,  H05K2203/0353 ,  H05K2203/072 ,  H05K2203/1407 ,  H05K3/064 ,  Y10S428/901 ,  Y10T428/24322 ,  Y10T428/24917

摘要： A process for making a circuitized substrate is defined wherein the substrate is treated with two different, e.g., additive and subtractive, metallization processes. The process is thus able to effectively produce substrates including conductive features, e. g., high density circuit lines and chip heat-sinking pads, of two different degrees of resolution in a cost effective and expeditious manner. The resulting product is also defined.

摘要翻译： 定义制造电路化衬底的方法，其中用两种不同的，例如添加和减去的金属化工艺处理衬底。 因此，该方法能够有效地产生包括导电特征的基底， 例如，高密度电路线和芯片散热垫，具有两种不同程度的分辨率，具有成本效益和快速的方式。 所得产品也被定义。

公开(公告)号：US5707893A

公开(公告)日：1998-01-13

申请号：US566363

申请日：1995-12-01

申请人： Anilkumar Chinuprasad Bhatt ,  Ashwinkumar Chinuprasad Bhatt ,  Robert Jeffrey Day ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight ,  Richard William Malek ,  Voya Rista Markovich

发明人： Anilkumar Chinuprasad Bhatt ,  Ashwinkumar Chinuprasad Bhatt ,  Robert Jeffrey Day ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight ,  Richard William Malek ,  Voya Rista Markovich

IPC分类号： H05K1/02 ,  H05K3/06 ,  H05K3/10 ,  H05K3/42 ,  H01L21/445

CPC分类号： H05K1/0265 ,  H05K3/108 ,  H05K3/428 ,  H05K1/0263 ,  H05K2201/0347 ,  H05K2201/09727 ,  H05K2203/0353 ,  H05K2203/072 ,  H05K2203/1407 ,  H05K3/064 ,  Y10S428/901 ,  Y10T428/24322 ,  Y10T428/24917

摘要： A process for making a circuitized substrate is defined wherein the substrate is treated with two different, e.g., additive and subtractive, metallization processes. The process is thus able to effectively produce substrates including conductive features, e.g., high density circuit lines and chip heat-sinking pads, of two different degrees of resolution in a cost effective and expeditious manner. The resulting product is also defined.

摘要翻译： 定义制造电路化衬底的方法，其中用两种不同的，例如添加和减去的金属化工艺处理衬底。 因此，该方法能够以成本有效和快速的方式有效地产生包括两种不同分辨率度的导电特征（例如，高密度电路线和芯片散热垫）的衬底。 所得产品也被定义。

公开(公告)号：US06038137A

公开(公告)日：2000-03-14

申请号：US870848

申请日：1997-06-06

申请人： Ashwinkumar Chinuprasad Bhatt ,  Subahu Dhirubhai Desai ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight

发明人： Ashwinkumar Chinuprasad Bhatt ,  Subahu Dhirubhai Desai ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight

IPC分类号： H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02

CPC分类号： H05K1/021 ,  H01L23/145 ,  H01L23/3677 ,  H01L23/49822 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/182 ,  H05K2201/09127 ,  H05K2201/09981 ,  H05K2203/049 ,  H05K3/0061 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.

摘要翻译： 公开了一种用于引线接合型芯片的芯片载体。 该芯片载体采用有机电介质材料，而不是常规的陶瓷材料。 该芯片载体还采用至少一个具有电镀光通孔的有机光可成像介质层，以电连接两个（或多个）扇出电路层。 该芯片载体还采用单层空腔来容纳芯片而不是多层腔，如常规的那样。 此外，该芯片载体包括直接在芯片下方的热通孔和/或金属层，以增强散热。

公开(公告)号：US5798909A

公开(公告)日：1998-08-25

申请号：US390344

申请日：1995-02-15

申请人： Ashwinkumar Chinuprasad Bhatt ,  Subahu Dhirubhai Desai ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight

发明人： Ashwinkumar Chinuprasad Bhatt ,  Subahu Dhirubhai Desai ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight

IPC分类号： H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02 ,  H01L23/488 ,  H05K7/20

CPC分类号： H05K1/021 ,  H01L23/145 ,  H01L23/3677 ,  H01L23/49822 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/182 ,  H05K2201/09127 ,  H05K2201/09981 ,  H05K2203/049 ,  H05K3/0061 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.

摘要翻译： 公开了一种用于引线接合型芯片的芯片载体。 该芯片载体采用有机电介质材料，而不是常规的陶瓷材料。 该芯片载体还采用至少一个具有电镀光通孔的有机光可成像介质层，以电连接两个（或多个）扇出电路层。 该芯片载体还采用单层空腔来容纳芯片而不是多层腔，如常规的那样。 此外，该芯片载体包括直接在芯片下方的热通孔和/或金属层，以增强散热。

公开(公告)号：US5724232A

公开(公告)日：1998-03-03

申请号：US655323

申请日：1996-05-21

申请人： Ashwinkumar Chinuprasad Bhatt ,  Subahu Dhirubhai Desai ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight

发明人： Ashwinkumar Chinuprasad Bhatt ,  Subahu Dhirubhai Desai ,  Thomas Patrick Duffy ,  Jeffrey Alan Knight

IPC分类号： H01L23/12 ,  H01L23/14 ,  H01L23/367 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K7/02 ,  H05K1/05 ,  H01L23/36

CPC分类号： H05K1/021 ,  H01L23/145 ,  H01L23/3677 ,  H01L23/49822 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/182 ,  H05K2201/09127 ,  H05K2201/09981 ,  H05K2203/049 ,  H05K3/0061 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A chip carrier for wire bond-type chips is disclosed. This chip carrier employs organic dielectric materials, rather than ceramic materials, as is conventional. This chip carrier also employs at least one organic, photoimageable dielectric layer, having plated photo-vias, to electrically interconnect two (or more) layers of fan-out circuitry. This chip carrier further employs a single-tiered cavity to contain a chip, rather than a multi-tiered cavity, as is conventional. Moreover, this chip carrier includes thermal via holes and/or a metallic layer, directly beneath the chip, to enhance heat dissipation.

摘要翻译： 公开了一种用于引线接合型芯片的芯片载体。 该芯片载体采用有机电介质材料，而不是常规的陶瓷材料。 该芯片载体还采用至少一个具有电镀光通孔的有机光可成像介质层，以电连接两个（或多个）扇出电路层。 该芯片载体还采用单层空腔来容纳芯片而不是多层腔，如常规的那样。 此外，该芯片载体包括直接在芯片下方的热通孔和/或金属层，以增强散热。

公开(公告)号：US5827386A

公开(公告)日：1998-10-27

申请号：US665184

申请日：1996-06-14

申请人： Ashwinkumar Chinuprasad Bhatt ,  Mark Daniel Derwin ,  Kenneth John Lubert

发明人： Ashwinkumar Chinuprasad Bhatt ,  Mark Daniel Derwin ,  Kenneth John Lubert

IPC分类号： H05K3/00 ,  H05K3/46 ,  H05K3/36

CPC分类号： H05K3/4623 ,  H05K3/0094 ,  H05K2203/1394

摘要： The ends of thru-holes, disposed in components that are laminated together to form a composite structure are masked prior to lamination of the components to prevent bonding material bleed through the holes during the lamination process. The method effectively solves the problem of the need to remove laminate bleed from the outer surface of the composite structure after the joining process.

摘要翻译： 设置在层叠在一起以形成复合结构的部件中的通孔的端部在层压部件之前被掩蔽，以防止在层压过程中粘合材料通过孔渗出。 该方法有效地解决了在接合过程之后从复合结构的外表面去除层压体渗出的问题。

公开(公告)号：US6127097A

公开(公告)日：2000-10-03

申请号：US819277

申请日：1997-03-18

申请人： Nageshwer Rao Bantu ,  Anilkumar Chinuprasad Bhatt ,  Ashwinkumar Chinuprasad Bhatt ,  Joseph Alphonse Kotylo ,  Gerald Walter Jones ,  Robert John Owen ,  Kostas Papathomas ,  Anaya Kumar Vardya

发明人： Nageshwer Rao Bantu ,  Anilkumar Chinuprasad Bhatt ,  Ashwinkumar Chinuprasad Bhatt ,  Joseph Alphonse Kotylo ,  Gerald Walter Jones ,  Robert John Owen ,  Kostas Papathomas ,  Anaya Kumar Vardya

IPC分类号： G03F7/32 ,  G03F7/42 ,  H05K3/06

CPC分类号： G03F7/422 ,  G03F7/325

摘要： Simple, environmentally friendly developers and strippers are disclosed for free radical-initiated, addition polymerizable resists, cationically cured resists and solder masks and photoresists. Both the developers and the strippers include benzyl alcohol, optionally also including a minor amount of methanol, ethanol, isopropyl alcohol, propylene glycol monomethylacetate, ethylene glycol monomethyl ether, formamide, nitromethane, propylene oxide, or methyl ethyl ketone, acetone and water.

摘要翻译： 公开了简单的，环保的显影剂和剥离剂，用于自由基引发的可加成聚合的抗蚀剂，阳离子固化的抗蚀剂和焊接掩模和光致抗蚀剂。 显影剂和脱模剂都包括苄醇，任选地还包括少量甲醇，乙醇，异丙醇，丙二醇单甲基乙酸酯，乙二醇单甲醚，甲酰胺，硝基甲烷，环氧丙烷或甲基乙基酮，丙酮和水。