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公开(公告)号：US5668831A
公开(公告)日：1997-09-16
申请号：US481107
申请日：1995-06-07
申请人： Anthony Peter J. Claydon , Charles D. MacFarlane , Richard J. Gammack , Anthony Mark Jones , William P. Robbins , Mark Barnes
发明人： Anthony Peter J. Claydon , Charles D. MacFarlane , Richard J. Gammack , Anthony Mark Jones , William P. Robbins , Mark Barnes
IPC分类号： H04N7/26 , H03H17/02 , H03H21/00 , H03K5/24 , H03M3/02 , H03M13/00 , H03M13/15 , H03M13/27 , H04B3/06 , H04L1/00 , H04L7/00 , H04L7/033 , H04L7/04 , H04L25/03 , H04L25/06 , H04L27/00 , H04L27/02 , H04L27/06 , H04L27/227 , H04L27/38 , H04N5/00 , H04N5/21 , H04N5/44 , H04N5/455 , H04N5/52 , H04N7/24 , H04N7/30 , H04N21/2383 , H04N21/438 , H03H7/30
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H03M13/2707 , H03M13/2764 , H04L1/0045 , H04L1/0071 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04L27/2273 , H04L27/3809 , H04N5/211 , H04N5/4401 , H04N5/4446 , H04N5/455 , H04N5/52 , H04L2027/0032 , H04L2027/0061 , H04L2027/0067 , H04L2027/0073 , H04L2027/0081 , H04L7/0334
摘要： An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes processing stages which demodulate, sample and filter the incoming signal prior to recovery of the digital data. Other stages recover the timing and lock on to the frequency and phase of the transmitted signal, as well as provide for automatic gain control. An adaptive equalizer, error correction circuitry, and an output interface recover the digital data and provide for transfer to other devices.
摘要翻译： 提供了利用多电平残留边带传输的集成数字通信系统。 通信系统从有限带宽信道接收多电平脉冲幅度调制数字信号。 该系统包括在恢复数字数据之前对输入信号进行解调，采样和滤波的处理阶段。 其他级恢复定时并锁定到发射信号的频率和相位，并提供自动增益控制。 自适应均衡器，纠错电路和输出接口恢复数字数据并提供传输到其他设备。
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公开(公告)号：US5910960A
公开(公告)日：1999-06-08
申请号：US480721
申请日：1995-06-07
申请人： Anthony Peter J. Claydon , Charles D. MacFarlane , Richard J. Gammack , Anthony Mark Jones , William P. Robbins , Mark Barnes
发明人： Anthony Peter J. Claydon , Charles D. MacFarlane , Richard J. Gammack , Anthony Mark Jones , William P. Robbins , Mark Barnes
CPC分类号： H04L1/0057 , H03K5/24 , H03M13/15 , H03M13/151 , H04L1/0045 , H04L25/03038 , H04L25/03866 , H04L25/062 , H04L27/02 , H04N21/4382 , H04N5/4446 , H04N5/4401
摘要： A CMOS Reed-Solomon decoding circuit calculates syndromes, executes a Berlekamp algorithm, performs a Chien Search, and corrects a delayed version of the received data according to a calculated magnitude of error. The circuit is optimized in terms of chip territory and circuit complexity. Signals are provided to indicate uncorrectable packet errors and other transmission errors.
摘要翻译： CMOS Reed-Solomon解码电路计算校正子，执行Berlekamp算法，执行Chien搜索，并根据计算的误差大小校正接收数据的延迟版本。 该电路在芯片领域和电路复杂性方面进行了优化。 提供信号以指示不可纠正的分组错误和其他传输错误。
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公开(公告)号：US06799246B1
公开(公告)日：2004-09-28
申请号：US08991234
申请日：1997-12-16
申请人： Adrian P. Wise , Kevin Douglas Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter J. Claydon , Donald W. Walker Patterson , Mark Barnes , Andrew Peter Kuligowski , William Philip Robbins , Nicholas Birch , David Andrew Barnes
发明人： Adrian P. Wise , Kevin Douglas Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter J. Claydon , Donald W. Walker Patterson , Mark Barnes , Andrew Peter Kuligowski , William Philip Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： G06F1208
CPC分类号： H04N21/4307 , G06F12/0207 , G06F12/04 , G06F13/16 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91 , H04N21/4305 , H04N21/44004
摘要： A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associated with the plurality of data words. The generator generates a series of addresses in the memory into which the buffered data words may be written. The series of addresses are derived from the received addresses. The writer writes the buffered data words into the memory at the generated addresses.
摘要翻译： 用于将总线连接到存储器的存储器接口包括输入，缓冲器，地址输入，发生器和写入器。 输入从总线接收多个数据字。 缓冲器缓冲从总线接收的数据字。 地址输入从与多个数据字相关联的总线地址接收。 发生器在存储器中产生一系列可以写入缓冲数据字的地址。 该地址系列从接收到的地址中导出。 写入器将生成的地址将缓冲的数据字写入存储器。
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公开(公告)号：US5768629A
公开(公告)日：1998-06-16
申请号：US479910
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
摘要翻译： 一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。 控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。 令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。 重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。 公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等 。
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公开(公告)号：US5835792A
公开(公告)日：1998-11-10
申请号：US487134
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
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公开(公告)号：US5829007A
公开(公告)日：1998-10-27
申请号：US486908
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： A RAM implementation of asynchronous swing buffering is provided in which two buffers are operated asynchronously; one is written while the other is read. Accordingly, this allows for a data stream having a fast rate of through-put to be resynchronized to another rate, while still maintaining a desired rate. In the invention, the write control and read control both have state indicators for communicating which buffer they are using and whether the controls are waiting for access or are, in fact, accessing that buffer.
摘要翻译： 提供了异步摆动缓冲的RAM实现，其中两个缓冲器是异步操作的; 一个是写在另一个被读取。 因此，这允许具有快速吞吐速率的数据流与另一个速率重新同步，同时仍然保持期望的速率。 在本发明中，写入控制和读取控制都具有用于通信它们正在使用哪个缓冲器的状态指示符，以及控制是否正在等待访问，或实际上访问该缓冲器。
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公开(公告)号：US5821885A
公开(公告)日：1998-10-13
申请号：US473813
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
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公开(公告)号：US5740460A
公开(公告)日：1998-04-14
申请号：US481772
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Adrian P. Wise , Kevin D. Dewar , Anthony Mark Jones , Martin William Sotheran , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , Mark Barnes , Andrew Peter Kuligowski , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52 , G06F15/66
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
摘要翻译： 一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。 控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。 令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。 重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。 公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等 。
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9.发明授权Multistandard video decoder and decompression system for processing encoded bit streams including a standard-independent stage and methods relating thereto 失效用于处理编码比特流的多标准视频解码器和解压缩系统，包括与标准无关的阶段和与之有关的方法公开(公告)号：US06892296B2
公开(公告)日：2005-05-10
申请号：US09773473
申请日：2001-02-01
申请人： Adrian P. Wise , Kevin Boyd , Anothy Peter Claydon , William P. Robbins , Helen R. Finch , Martin W. Sotheran , Anthony Mark Jones
发明人： Adrian P. Wise , Kevin Boyd , Anothy Peter Claydon , William P. Robbins , Helen R. Finch , Martin W. Sotheran , Anthony Mark Jones
IPC分类号： G06F7/00 , G06F9/38 , G06F9/44 , G06F12/02 , G06F12/04 , G06F12/06 , G06F13/16 , G06F13/28 , G06T9/00 , H04N7/26 , H04N7/50 , G06F15/00 , G06F7/08 , G06F7/24 , G06F7/36
CPC分类号： G06F9/3867 , G06F9/4494 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/16 , G06F13/1673 , G06F13/1689 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number. A token decode circuit positioned in certain of the stages recognizes certain of the tokens as control tokens pertinent to that stage and passes unrecognized control tokens to a succeeding stage. A reconfigurable decode and parser processing means positioned in certain of the stages is responsive to a recognized control token and reconfigures a particular stage to handle an identified data token. Methods relating to the decoder and decompression system include processing steps relating thereto.
摘要翻译： 流水线视频解码器和解压缩系统处理多个单独编码的比特流，其被布置为数字比特的单个串行比特流，并且具有单独编码的控制码对和串行比特流中携带的对应数据。 流水线系统采用多个互连的级来解码和解压缩单个比特流，包括起始码检测器。 当处于搜索模式时，起始代码检测器搜索与多个压缩标准之一相对应的特定开始代码。 响应于单个串行比特流的起始码检测器产生控制令牌和数据令牌。 相应的令牌包括多个数据字。 每个数据字具有指示其中存在附加字的扩展位。 因此数据字数量无限。 定位在某些阶段的令牌解码电路将某些令牌识别为与该级相关的控制令牌，并将未被识别的控制令牌传递到后续级。 定位在某些阶段的可重构解码和解析器处理装置响应于识别的控制令牌，并且重新配置特定级以处理所识别的数据令牌。 与解码器和解压缩系统相关的方法包括与其相关的处理步骤。
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公开(公告)号：US5984512A
公开(公告)日：1999-11-16
申请号：US488348
申请日：1995-06-07
申请人： Anthony Mark Jones , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , William P. Robbins , Nicholas Birch , David Andrew Barnes
发明人： Anthony Mark Jones , Colin Smith , Helen Rosemary Finch , Anthony Peter John Claydon , Donald William Patterson , William P. Robbins , Nicholas Birch , David Andrew Barnes
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52 , G06F17/00
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in select stages and are responsive to a recognized control token for reconfiguring such stages to handle an identified DATA Token. A wide variety of unique supporting subsystems circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
摘要翻译： 一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。 控制令牌和数据令牌通过单个双线接口，用于携带控制和令牌格式。 令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。 重新配置处理电路位于选择阶段，并响应于识别的控制令牌，以重新配置这些阶段来处理所识别的数据令牌。 公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等 。
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