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公开(公告)号:US12300554B2
公开(公告)日:2025-05-13
申请号:US18349930
申请日:2023-07-10
Applicant: Applied Materials, Inc.
Inventor: Mandar B. Pandit , Man-Ping Cai , Wenhui Li , Michael Wenyoung Tsiang , Praket Prakash Jha , Jingmin Leng
Abstract: Embodiments of the present technology may include semiconductor processing methods that include depositing a film of semiconductor material on a substrate in a substrate processing chamber. The deposited film may be sampled for defects at greater than or about two non-contiguous regions of the substrate with scanning electron microscopy. The defects that are detected and characterized may include those of a size less than or about 10 nm. The methods may further include calculating a total number of defects in the deposited film based on the sampling for defects in the greater than or about two non-contiguous regions of the substrate. At least one deposition parameter may be adjusted as a result of the calculation. The adjustment to the at least one deposition parameter may reduce the total number of defects in a deposition of the film of semiconductor material.
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公开(公告)号:US11699623B2
公开(公告)日:2023-07-11
申请号:US17070751
申请日:2020-10-14
Applicant: Applied Materials, Inc.
Inventor: Mandar B. Pandit , Man-Ping Cai , Wenhui Li , Michael Wenyoung Tsiang , Praket Prakash Jha , Jingmin Leng
CPC classification number: H01L22/20 , C23C16/401 , C23C16/52 , H01L21/02164 , H01L21/67288
Abstract: Embodiments of the present technology may include semiconductor processing methods that include depositing a film of semiconductor material on a substrate in a substrate processing chamber. The deposited film may be sampled for defects at greater than or about two non-contiguous regions of the substrate with scanning electron microscopy. The defects that are detected and characterized may include those of a size less than or about 10 nm. The methods may further include calculating a total number of defects in the deposited film based on the sampling for defects in the greater than or about two non-contiguous regions of the substrate. At least one deposition parameter may be adjusted as a result of the calculation. The adjustment to the at least one deposition parameter may reduce the total number of defects in a deposition of the film of semiconductor material.
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公开(公告)号:US20220375747A1
公开(公告)日:2022-11-24
申请号:US17325764
申请日:2021-05-20
Applicant: Applied Materials, Inc.
Inventor: Wenhui Li , Praket P. Jha , Mandar B. Pandit , Man-Ping Cai , Jingmei Liang , Michael Wenyoung Tsiang
IPC: H01L21/02
Abstract: Processing methods disclosed herein comprise forming a nucleation layer and a flowable chemical vapor deposition (FCVD) film on a substrate surface by exposing the substrate surface to a silicon-containing precursor and a reactant. By controlling at least one of a precursor/reactant pressure ratio, a precursor/reactant flow ratio and substrate temperature formation of miniature defects is minimized. Controlling at least one of the process parameters may reduce the number of miniature defects. The FCVD film can be cured by any suitable curing process to form a smooth FCVD film.
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公开(公告)号:US20190311900A1
公开(公告)日:2019-10-10
申请号:US15949341
申请日:2018-04-10
Applicant: Applied Materials, Inc.
Inventor: Mandar B. Pandit , Mang-Mang Ling , Tom Choi , Nitin K. Ingle
IPC: H01L21/033 , H01L21/311 , H01L21/67
Abstract: Methods may be performed to limit footing, pitch walking, and other alignment issues. The methods may include forming a treatment gas plasma within a processing region of a semiconductor processing chamber. The methods may further include directing effluents of the treatment gas plasma towards a semiconductor substrate within the processing region of the semiconductor processing chamber, and anisotropically modifying a surface of a first material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may also include passivating a surface of a second material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may further include forming a remote fluorine-containing plasma to produce fluorine-containing plasma effluents, and flowing the fluorine-containing plasma effluents to the processing region of the semiconductor processing chamber. The methods may also include selectively removing the modified surface of the first material from the semiconductor substrate.
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公开(公告)号:US20230352349A1
公开(公告)日:2023-11-02
申请号:US18349930
申请日:2023-07-10
Applicant: Applied Materials, Inc.
Inventor: Mandar B. Pandit , Man-Ping Cai , Wenhui Li , Michael Wenyoung Tsiang , Praket Prakash Jha , Jingmin Leng
CPC classification number: H01L22/20 , H01L21/02164 , C23C16/52 , C23C16/401 , H01L21/67288
Abstract: Embodiments of the present technology may include semiconductor processing methods that include depositing a film of semiconductor material on a substrate in a substrate processing chamber. The deposited film may be sampled for defects at greater than or about two non-contiguous regions of the substrate with scanning electron microscopy. The defects that are detected and characterized may include those of a size less than or about 10 nm. The methods may further include calculating a total number of defects in the deposited film based on the sampling for defects in the greater than or about two non-contiguous regions of the substrate. At least one deposition parameter may be adjusted as a result of the calculation. The adjustment to the at least one deposition parameter may reduce the total number of defects in a deposition of the film of semiconductor material.
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公开(公告)号:US20220115275A1
公开(公告)日:2022-04-14
申请号:US17070751
申请日:2020-10-14
Applicant: Applied Materials, Inc.
Inventor: Mandar B. Pandit , Man-Ping Cai , Wenhui Li , Michael Wenyoung Tsiang , Praket Prakash Jha , Jingmin Leng
Abstract: Embodiments of the present technology may include semiconductor processing methods that include depositing a film of semiconductor material on a substrate in a substrate processing chamber. The deposited film may be sampled for defects at greater than or about two non-contiguous regions of the substrate with scanning electron microscopy. The defects that are detected and characterized may include those of a size less than or about 10 nm. The methods may further include calculating a total number of defects in the deposited film based on the sampling for defects in the greater than or about two non-contiguous regions of the substrate. At least one deposition parameter may be adjusted as a result of the calculation. The adjustment to the at least one deposition parameter may reduce the total number of defects in a deposition of the film of semiconductor material.
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公开(公告)号:US20180096843A1
公开(公告)日:2018-04-05
申请号:US15816520
申请日:2017-11-17
Applicant: Applied Materials, Inc.
Inventor: Prashant Kumar Kulshreshtha , Sudha Rathi , Praket P. Jha , Saptarshi Basu , Kwangduk Douglas Lee , Martin J. Seamons , Bok Hoen Kim , Ganesh Balasubramanian , Ziqing Duan , Lei Jing , Mandar B. Pandit
IPC: H01L21/02 , C23C16/04 , H01L21/311 , H01L21/66 , C23C16/26 , C23C16/455 , C23C16/458 , C23C16/46 , H01L21/033
CPC classification number: H01L21/02274 , C23C16/04 , C23C16/26 , C23C16/455 , C23C16/45502 , C23C16/45508 , C23C16/45565 , C23C16/458 , C23C16/4584 , C23C16/4586 , C23C16/46 , H01L21/02115 , H01L21/0337 , H01L21/31144 , H01L22/12
Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.
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公开(公告)号:US09721784B2
公开(公告)日:2017-08-01
申请号:US14770412
申请日:2014-02-14
Applicant: Applied Materials, Inc.
Inventor: Swayambhu P. Behera , Shahid Shaikh , Pramit Manna , Mandar B. Pandit , Tersem Summan , Patrick Reilly , Deenesh Padhi , Bok Hoen Kim , Heung Lak Park , Derek R. Witty
IPC: H01L21/02 , H01L21/033 , H01L21/311 , C23C16/26 , C23C16/50
CPC classification number: H01L21/02115 , C23C16/26 , C23C16/50 , H01L21/02274 , H01L21/0337 , H01L21/31116
Abstract: Embodiments of the invention relate to deposition of a conformal carbon-based material. In one embodiment, the method comprises depositing a sacrificial dielectric layer with a predetermined thickness over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, introducing a hydrocarbon source, a plasma-initiating gas, and a dilution gas into the processing chamber, wherein a volumetric flow rate of hydrocarbon source:plasma-initiating gas:dilution gas is in a ratio of 1:0.5:20, generating a plasma at a deposition temperature of about 300 C to about 500 C to deposit a conformal amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate, and removing the patterned features.
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公开(公告)号:US09343272B1
公开(公告)日:2016-05-17
申请号:US14592509
申请日:2015-01-08
Applicant: Applied Materials, Inc.
Inventor: Mandar B. Pandit , Anchuan Wang , Nitin K. Ingle
IPC: H01J37/32 , H01L21/3065
CPC classification number: H01J37/32412 , H01J37/32357 , H01L21/3065 , H01L21/31116 , H01L21/31155 , H01L21/76825 , H01L21/76897
Abstract: Methods of forming self-aligned structures on patterned substrates are described. The methods may be used to form metal lines or vias without the use of a separate photolithography pattern definition operation. Self-aligned contacts may be produced regardless of the presence of spacer elements. The methods include directionally ion-implanting a gapfill portion of a gapfill silicon oxide layer to implant into the gapfill portion without substantially ion-implanting the remainder of the gapfill silicon oxide layer (the sidewalls). Subsequently, a remote plasma is formed using a fluorine-containing precursor to etch the patterned substrate such that the gapfill portions of silicon oxide are selectively etched relative to other exposed portions exposed parallel to the ion implantation direction. Without ion implantation, the etch operation would be isotropic owing to the remote nature of the plasma excitation during the etch process.
Abstract translation: 描述了在图案化衬底上形成自对准结构的方法。 该方法可用于形成金属线或通孔而不使用单独的光刻图案定义操作。 可以产生自对准的触点,而不管间隔元件的存在。 所述方法包括定向地离子注入间隙填充氧化硅层的间隙填充部分以注入到间隙填充部分中,而基本上不离子注入间隙填充氧化硅层(侧壁)的剩余部分。 随后,使用含氟前体形成远程等离子体以蚀刻图案化衬底,使得相对于平行于离子注入方向暴露的其它暴露部分选择性地蚀刻氧化硅的间隙填充部分。 在没有离子注入的情况下,蚀刻操作将是各向同性的,这是由于在蚀刻过程期间等离子体激发的远程特性。
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公开(公告)号:US20200043734A1
公开(公告)日:2020-02-06
申请号:US16599447
申请日:2019-10-11
Applicant: Applied Materials, Inc.
Inventor: Mandar B. Pandit , Mang-Mang Ling , Tom Choi , Nitin K. Ingle
IPC: H01L21/033 , H01L21/311 , H01L21/67
Abstract: Methods may be performed to limit footing, pitch walking, and other alignment issues. The methods may include forming a treatment gas plasma within a processing region of a semiconductor processing chamber. The methods may further include directing effluents of the treatment gas plasma towards a semiconductor substrate within the processing region of the semiconductor processing chamber, and anisotropically modifying a surface of a first material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may also include passivating a surface of a second material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may further include forming a remote fluorine-containing plasma to produce fluorine-containing plasma effluents, and flowing the fluorine-containing plasma effluents to the processing region of the semiconductor processing chamber. The methods may also include selectively removing the modified surface of the first material from the semiconductor substrate.
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