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    Gang flipping for IC packaging
    1.
    发明授权
    Gang flipping for IC packaging 有权
    帮派翻转用于IC封装

    公开(公告)号：US07491625B2

    公开(公告)日：2009-02-17

    申请号：US11691431

    申请日：2007-03-26

    申请人： Jaime A. Bayan ,  Nghia Tu ,  Anindya Poddar ,  Ashok Prabhu

    发明人： Jaime A. Bayan ,  Nghia Tu ,  Anindya Poddar ,  Ashok Prabhu

    IPC分类号： H01L21/00

    CPC分类号： H01L21/6835 ,  H01L21/6836 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/16 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/0401

    摘要： A method of handling an IC wafer that includes a multiplicity of dice is described. Solder bumps are formed on bond pads on the active surface of the wafer. The back surface of the bumped wafer is adhered to a first mount tape. The wafer is singulated while it is still secured to the first tape to provide a multiplicity of individual dice. The active surfaces of the singulated dice are then adhered to a second tape with the first tape still adhered to the back surfaces of the dice. The first tape may then be removed. In this manner, the back surfaces of the dice may be left exposed and facing upwards with the active surfaces of the dice adhered to the second tape. The described method permits the use of a conventional die attach machine that is not designated for use as a flip-chip die attach machine.

    摘要翻译： 描述了处理包括多个骰子的IC晶片的方法。 焊料凸起形成在晶片的有源表面上的接合焊盘上。 凸起的晶片的背面粘附到第一安装带。 在晶片仍被固定到第一磁带的同时将晶片单片化以提供多个独立的骰子。 然后将分割的骰子的活性表面粘附到第二带上，其中第一带仍然粘附到骰子的后表面。 然后可以移除第一个磁带。 以这种方式，骰子的后表面可以被暴露并且面向上并且骰子的活动表面粘附到第二带上。 所描述的方法允许使用未被指定用作倒装芯片连接机的常规的芯片连接机。

    GANG FLIPPING FOR IC PACKAGING
    3.
    发明申请
    GANG FLIPPING FOR IC PACKAGING 有权
    缉拿包装IC

    公开(公告)号：US20080241993A1

    公开(公告)日：2008-10-02

    申请号：US11691431

    申请日：2007-03-26

    申请人： Jaime A. Bayan ,  Nghia Tu ,  Anindya Poddar ,  Ashok Prabhu

    发明人： Jaime A. Bayan ,  Nghia Tu ,  Anindya Poddar ,  Ashok Prabhu

    IPC分类号： H01L21/58

    CPC分类号： H01L21/6835 ,  H01L21/6836 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/16 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/0401

    摘要： A method of handling an IC wafer that includes a multiplicity of dice is described. Solder bumps are formed on bond pads on the active surface of the wafer. The back surface of the bumped wafer is adhered to a first mount tape. The wafer is singulated while it is still secured to the first tape to provide a multiplicity of individual dice. The active surfaces of the singulated dice are then adhered to a second tape with the first tape still adhered to the back surfaces of the dice. The first tape may then be removed. In this manner, the back surfaces of the dice may be left exposed and facing upwards with the active surfaces of the dice adhered to the second tape. The described method permits the use of a conventional die attach machine that is not designated for use as a flip-chip die attach machine.

    摘要翻译： 描述了处理包括多个骰子的IC晶片的方法。 焊料凸起形成在晶片的有源表面上的接合焊盘上。 凸起晶片的背面粘附到第一安装带。 在晶片仍被固定到第一磁带的同时将晶片单片化以提供多个独立的骰子。 然后将分割的骰子的活性表面粘附到第二带上，其中第一带仍然粘附到骰子的后表面。 然后可以移除第一个磁带。 以这种方式，骰子的后表面可以被暴露并且面向上并且骰子的活动表面粘附到第二带上。 所描述的方法允许使用未被指定用作倒装芯片连接机的常规的芯片连接机。

    Process and structure improvements to shellcase style packaging technology
    4.
    发明授权
    Process and structure improvements to shellcase style packaging technology 有权
    外壳式包装技术的工艺和结构改进

    公开(公告)号：US06607941B2

    公开(公告)日：2003-08-19

    申请号：US10044805

    申请日：2002-01-11

    申请人： Ashok Prabhu ,  Nikhil Kelkar ,  Anindya Poddar

    发明人： Ashok Prabhu ,  Nikhil Kelkar ,  Anindya Poddar

    IPC分类号： H01L2144

    CPC分类号： H01L23/3135 ,  H01L23/3114 ,  H01L23/49805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A variety of improved shell case style packages as well as shell case style wafer level packaging processes are described. Generally, in shell case style packaging, traces are patterned on the top surface of a wafer. In some embodiments, the conductors formed along the sides of the package are formed from at least a couple conductor layers to improve the adhesion of the conductors to the traces formed on the top surface of the devices. In some embodiments the conductors are patterned during processing such that the conductors are not cut during the wafer dicing operation. This arrangement is particularly useful when the conductors are formed at least partially from aluminum (or other metals that oxidize in ambient air). In other embodiments, BCB is not used under the trace layer in regions that will have notches formed therein so that the resulting package does not have any exposed BCB/trace junctions. In some embodiments, no BCB layer whatsoever is applied during packaging. In other embodiments, BCB is used, but the BCB layer is patterned to avoid dice line areas that will later be trenched or notched.

    摘要翻译： 描述了各种改进的壳壳式包装以及壳壳式晶片级封装工艺。 通常，在外壳外壳型封装中，迹线图案化在晶片的顶表面上。 在一些实施例中，沿着封装的侧面形成的导体由至少一对导体层形成，以改善导体与形成在器件的顶表面上的迹线的粘附。 在一些实施例中，在处理过程中导体被图案化，使得导体在晶片切割操作期间不被切割。 当导体至少部分地由铝（或在环境空气中氧化的其它金属）形成时，这种布置是特别有用的。 在其它实施例中，BCB不在其中形成有缺口的区域中的迹线层下使用，使得所得到的封装不具有任何暴露的BCB /迹线结。 在一些实施例中，在包装期间不施加任何BCB层。 在其他实施例中，使用BCB，但是BCB层被图案化以避免稍后将被沟槽或切口的骰子线区域。

    MICRO SURFACE MOUNT DEVICE PACKAGING
    6.
    发明申请
    MICRO SURFACE MOUNT DEVICE PACKAGING 审中-公开
    微表面装置包装

    公开(公告)号：US20130127044A1

    公开(公告)日：2013-05-23

    申请号：US13303073

    申请日：2011-11-22

    申请人： Anindya Poddar ,  Tao Feng ,  Will K. Wong

    发明人： Anindya Poddar ,  Tao Feng ,  Will K. Wong

    IPC分类号： H01L23/488 ,  H01L21/78

    CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/568 ,  H01L23/13 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/157 ,  H01L2924/15724 ,  H01L2924/1579 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

    摘要： A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of die cavities are formed in a plastic carrier. In some preferred embodiments, the die cavities are formed by laser ablation. A multiplicity of dice are placed on the carrier, with each die being placed in an associated die cavity. Each of the dice preferably has a multiplicity of I/O bumps formed thereon. An encapsulant is applied over the carrier to form an encapsulant layer that covers the dice and fills portions of the cavities that are not occupied by the dice. In some preferred embodiments, the encapsulant is an epoxy material applied by screen printing and the dice are not physically attached to the carrier prior to the application of the encapsulant. In these embodiments, the epoxy encapsulant serves to secure the dice to the carrier.

    摘要翻译： 描述了用于封装集成电路的各种改进方法。 在一种所描述的方法中，在塑料载体中形成多个模腔。 在一些优选实施例中，模腔通过激光烧蚀形成。 将多个骰子放置在载体上，每个模具被放置在相关的模腔中。 每个骰子优选地具有形成在其上的多个I / O凸块。 将密封剂施加在载体上以形成覆盖骰子并填充未被骰子占据的空腔的部分的密封剂层。 在一些优选的实施方案中，密封剂是通过丝网印刷施加的环氧材料，并且在施加密封剂之前，骰子不物理附着到载体上。 在这些实施例中，环氧树脂密封剂用于将骰子固定到载体上。

    Foil based semiconductor package
    7.
    发明授权
    Foil based semiconductor package 有权
    箔基半导体封装

    公开(公告)号：US08101470B2

    公开(公告)日：2012-01-24

    申请号：US12571202

    申请日：2009-09-30

    申请人： Anindya Poddar ,  Nghia Thuc Tu ,  Jaime Bayan ,  Will Wong ,  David Chin

    发明人： Anindya Poddar ,  Nghia Thuc Tu ,  Jaime Bayan ,  Will Wong ,  David Chin

    IPC分类号： H01L23/28 ,  H01L21/56

    CPC分类号： H01L23/3107 ,  H01L21/568 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2924/00

    摘要： The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages.

    摘要翻译： 本发明涉及使用薄箔在集成电路封装中形成电互连的方法和布置。 本发明的一个实施例涉及将多个骰子附接到箔片载体结构。 箔载体结构由结合到载体的薄箔制成。 然后将模具和至少一部分金属箔用模制材料包封。 移除载体，留下模制的箔结构。 使用光刻技术对暴露的箔进行图案化和蚀刻，以在箔中限定多个器件区域。 每个设备区域包括多条导线。 之后，导电线的一部分被电介质材料覆盖，并且其它部分被暴露以在器件区域中限定多个接合焊盘。 模制的箔结构可以被单个化以形成多个集成电路封装。

    Inkjet printed leadframes
    9.
    发明授权
    Inkjet printed leadframes 有权
    喷墨打印引线框

    公开(公告)号：US07667304B2

    公开(公告)日：2010-02-23

    申请号：US12110991

    申请日：2008-04-28

    申请人： Randall L. Walberg ,  Luu T. Nguyen ,  Anindya Poddar

    发明人： Randall L. Walberg ,  Luu T. Nguyen ,  Anindya Poddar

    IPC分类号： H01L23/495 ,  H01L21/44

    CPC分类号： H01L21/4821 ,  H01L21/6835 ,  H01L23/49579 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2924/14 ,  H01L2924/00

    摘要： Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays.

    摘要翻译： 公开了用于集成电路装置的用于喷墨印刷电互连图案的引线框架的装置和方法。 一种用于包装的装置包括适于高温处理的薄基板，以及使用金属纳米接头喷墨印刷到薄基板上的连接焊盘和接触区域。 然后将nanoink固化以除去液体内容物。 剩余的金属引线框架或电互连图案具有约10至50微米或更小的基本一致的厚度。 相关联的面板组件包括导电衬底面板，该导电衬底面板具有多个单独的器件阵列，每个单独的器件阵列包括多个电互连图案，每个均包括安装在导电衬底面板上的多个集成电路器件，以及封装集成电路器件和相关联的电互连图案的模制帽。 模制帽在每个分离的装置阵列上具有基本均匀的厚度，并且延伸到分离的装置阵列之间的空间中。

    INKJET PRINTED LEADFRAMES
    10.
    发明申请
    INKJET PRINTED LEADFRAMES 有权

    公开(公告)号：US20090267216A1

    公开(公告)日：2009-10-29

    申请号：US12110991

    申请日：2008-04-28

    申请人： Randall L. Walberg ,  Luu T. Nguyen ,  Anindya Poddar

    发明人： Randall L. Walberg ,  Luu T. Nguyen ,  Anindya Poddar

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/4821 ,  H01L21/6835 ,  H01L23/49579 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2924/14 ,  H01L2924/00

    摘要： Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays.

    摘要翻译： 公开了用于集成电路装置的用于喷墨印刷电互连图案的引线框架的装置和方法。 一种用于包装的装置包括适于高温处理的薄基板，以及使用金属纳米接头喷墨印刷到薄基板上的连接焊盘和接触区域。 然后将nanoink固化以除去液体内容物。 剩余的金属引线框架或电互连图案具有约10至50微米或更小的基本一致的厚度。 相关联的面板组件包括导电衬底面板，该导电衬底面板具有多个单独的器件阵列，每个器件阵列包括多个电互连图案，每个电连接图案，安装在导电衬底面板上的多个集成电路器件，以及封装集成电路器件和相关电气互连图案的模制帽。 模制帽在每个分离的装置阵列上具有基本均匀的厚度，并且延伸到分离的装置阵列之间的空间中。