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    Apparatus and method for packaging image sensing semiconductor chips
    1.
    发明授权
    Apparatus and method for packaging image sensing semiconductor chips 有权
    用于封装图像感测半导体芯片的装置和方法

    公开(公告)号：US07205095B1

    公开(公告)日：2007-04-17

    申请号：US10666921

    申请日：2003-09-17

    申请人： Ashok Prabhu ,  Shaw Wei Lee

    发明人： Ashok Prabhu ,  Shaw Wei Lee

    IPC分类号： G03C5/00 ,  H01L31/0203

    CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An method and apparatus for fabricating a die having imaging circuitry and fabricating a lid having a transparent region and support regions having a predetermined height. The lid is fabricated by applying a photo-sensitive adhesive layer with a thickness substantially equal to the predetermined height to a transparent plate and patterning the photo-sensitive adhesive layer to form the transparent region and the support regions. Once fabrication of the lid is complete, it is mounted directly onto the die so that the transparent region generally covers the imaging circuitry. The resulting apparatus includes a lid mounted directly onto the die with the transparent region generally positioned above the imaging circuitry. A gap, having a height dimension substantially equal to the predetermined height of the support regions of the lid, is spaced between the transparent region of the lid and the imaging circuitry on the die.

    摘要翻译： 一种用于制造具有成像电路并具有透明区域的盖子和具有预定高度的支撑区域的模具的方法和装置。 通过将具有基本上等于预定高度的厚度的光敏粘合剂层施加到透明板并图案化光敏粘合剂层以形成透明区域和支撑区域来制造盖。 一旦盖的制造完成，就将其直接安装在模具上，使得透明区域通常覆盖成像电路。 所得到的装置包括直接安装在模具上的盖，透明区域通常位于成像电路的上方。 具有基本上等于盖的支撑区域的预定高度的高度尺寸的间隙在盖的透明区域和模具上的成像电路之间间隔开。

    Apparatus and method for wafer level packaging of optical imaging semiconductor devices
    2.
    发明授权
    Apparatus and method for wafer level packaging of optical imaging semiconductor devices 有权
    光学成像半导体器件的晶片级封装的装置和方法

    公开(公告)号：US06873024B1

    公开(公告)日：2005-03-29

    申请号：US10217341

    申请日：2002-08-09

    申请人： Ashok Prabhu ,  Shaw Wei Lee

    发明人： Ashok Prabhu ,  Shaw Wei Lee

    IPC分类号： H01L31/0203 ,  H01L31/0232 ,  H01L23/02 ,  H01L23/24

    CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L27/14625 ,  H01L2224/48465 ,  H01L2224/48091 ,  H01L2924/00014

    摘要： An apparatus and method for wafer level packaging of optical imaging die using conventional semiconductor packaging techniques. The method comprises forming spacing structures over imaging circuitry on a plurality of dice on a semiconductor wafer, attaching a transparent template on the spacing structures on the plurality dice on the semiconductor wafer, singulating the plurality of dice on the semiconductor wafer, and packaging the plurality of dice after being singulated from the wafer. The apparatus comprises a semiconductor wafer including a plurality of dice, each of the dice including imaging circuitry and bond pads. A translucent template is positioned over the semiconductor wafer. The translucent plate includes die cover regions configured to cover the imaging circuitry of the dice and recess regions to exposed the bond pads of the dice respectively. The resulting chip, after further packaging steps, includes the substrate, the semiconductor die having imaging circuitry and bond pads, the semiconductor die mounted onto the substrate and the transparent template positioned over the semiconductor die. The transparent template includes the a die cover region configured to be positioned over the imaging circuitry of the semiconductor die and recess regions to expose the bond pads of the semiconductor die.

    摘要翻译： 一种用于使用常规半导体封装技术的光学成像芯片的晶片级封装的装置和方法。 该方法包括在半导体晶片上的多个骰子上的成像电路上形成间隔结构，在半导体晶片上的多个骰子上的间隔结构上附加透明模板，在半导体晶片上分离多个骰子，并将多个骰子 在从晶片分离后的骰子。 该装置包括包括多个骰子的半导体晶片，每个骰子包括成像电路和接合焊盘。 半透明模板位于半导体晶片上方。 半透明板包括被配置为覆盖骰子和凹陷区域的成像电路的裸片盖区域，以分别露出骰子的接合焊盘。 所得到的芯片在进一步的封装步骤之后包括衬底，具有成像电路和接合焊盘的半导体管芯，安装在衬底上的半导体管芯和位于半导体管芯上方的透明模板。 透明模板包括被配置为定位在半导体管芯的成像电路上方的裸片盖区域和凹部区域以露出半导体管芯的接合焊盘。

    Electrical die contact structure and fabrication method
    3.
    发明授权
    Electrical die contact structure and fabrication method 有权
    电模接触结构及制造方法

    公开(公告)号：US07340181B1

    公开(公告)日：2008-03-04

    申请号：US10145295

    申请日：2002-05-13

    申请人： Ashok Prabhu ,  Sadanand R. Patil ,  Shaw Wei Lee ,  Alexander H. Owens

    发明人： Ashok Prabhu ,  Sadanand R. Patil ,  Shaw Wei Lee ,  Alexander H. Owens

    IPC分类号： H04B10/00

    CPC分类号： H01L27/14618 ,  H01L23/482 ,  H01L23/4827 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The second surface of the semiconductor substrate includes a bottom protective layer with electrical connectors. The surface portion of the top protective layer includes electrical contact pads that are electrically interconnected with electrical contact pad extensions. The electrical contact pad extensions are interconnected with electrical connectors via a backside electrical connector that overlaps the electrical contact pad extensions forming a lap connection. Methods for constructing such devices and connections are also disclosed.

    摘要翻译： 本发明的半导体器件包括形成在具有第一和第二表面的半导体衬底上的集成电路和沿着边缘的切口区域。 第一表面包括与集成电路电连接的电接触垫。 半导体衬底的第一表面包括具有延伸超过半导体衬底的边缘的表面部分的顶部保护层。 半导体衬底的第二表面包括具有电连接器的底部保护层。 顶部保护层的表面部分包括与电接触焊盘延伸部电互连的电接触焊盘。 电接触焊盘延伸部经由背面电连接器与电连接器互连，后侧电连接器与形成搭接连接的电接触垫延伸部重叠。 还公开了用于构造这种装置和连接的方法。

    Electrical die contact structure and fabrication method
    4.
    发明授权
    Electrical die contact structure and fabrication method 有权
    电模接触结构及制造方法

    公开(公告)号：US07795126B2

    公开(公告)日：2010-09-14

    申请号：US11969756

    申请日：2008-01-04

    申请人： Ashok Prabhu ,  Sadanand R. Patil ,  Shaw Wei Lee ,  Alexander H. Owens

    发明人： Ashok Prabhu ,  Sadanand R. Patil ,  Shaw Wei Lee ,  Alexander H. Owens

    IPC分类号： H01L21/00 ,  H01L21/44

    CPC分类号： H01L27/14618 ,  H01L23/482 ,  H01L23/4827 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and a notch region along the edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The second surface of the semiconductor substrate includes a bottom protective layer with electrical connectors. The surface portion of the top protective layer includes electrical contact pads that are electrically interconnected with electrical contact pad extensions. The electrical contact pad extensions are interconnected with electrical connectors via a backside electrical connector that overlaps the electrical contact pad extensions forming a lap connection. Methods for constructing such devices and connections are also disclosed.

    摘要翻译： 本发明的半导体器件包括形成在具有第一和第二表面的半导体衬底上的集成电路和沿着边缘的切口区域。 第一表面包括与集成电路电连接的电接触垫。 半导体衬底的第一表面包括具有延伸超过半导体衬底的边缘的表面部分的顶部保护层。 半导体衬底的第二表面包括具有电连接器的底部保护层。 顶部保护层的表面部分包括与电接触焊盘延伸部电互连的电接触焊盘。 电接触焊盘延伸部经由背面电连接器与电连接器互连，后侧电连接器与形成搭接连接的电接触垫延伸部重叠。 还公开了用于构造这种装置和连接的方法。

    Known good die test apparatus and method
    7.
    发明授权
    Known good die test apparatus and method 失效
    已知的好的模具试验装置和方法

    公开(公告)号：US5686842A

    公开(公告)日：1997-11-11

    申请号：US521619

    申请日：1995-08-31

    申请人： Shaw Wei Lee

    发明人： Shaw Wei Lee

    IPC分类号： G01R1/073

    CPC分类号： G01R1/07357

    摘要： An apparatus and method for testing an integrated circuit chip prior to mounting on a package including a non-conductive tape upon which are formed a plurality of contacts arranged in a pattern matching the arrangement of bonding pads of an integrated circuit, and a z-axis conductor placed over the conductive tape. The target chip is placed on the z-axis conductor and test signals are transmitted between the contacts on the tape and the bonding pads of the integrated circuit through conductors embedded in the z-axis conductor. In one embodiment, a glass or ceramic plate including openings, arranged in the same pattern as the bonding pads, is placed between the integrated circuit and the z-axis conductor to prevent damage to the integrated circuit.

    摘要翻译： 一种用于在安装在包括非导电胶带的包装上的集成电路芯片测试的装置和方法，在该封装上形成多个以与集成电路的接合焊盘的布置匹配的图案布置的触点，以及z轴 导体放置在导电胶带上。 目标芯片放置在z轴导体上，测试信号通过嵌入在z轴导体中的导体在磁带上的触点和集成电路的焊盘之间传输。 在一个实施例中，包括以与接合焊盘相同的图案的开口的玻璃或陶瓷板被放置在集成电路和z轴导体之间，以防止对集成电路的损坏。

    Substrate strips for use in integrated circuit packaging
    9.
    发明授权
    Substrate strips for use in integrated circuit packaging 有权
    用于集成电路封装的基板条

    公开(公告)号：US06278618B1

    公开(公告)日：2001-08-21

    申请号：US09416276

    申请日：1999-10-14

    申请人： Shaw Wei Lee ,  Anindya Poddar ,  Ram Veeraraghavan ,  Thanh Lequang

    发明人： Shaw Wei Lee ,  Anindya Poddar ,  Ram Veeraraghavan ,  Thanh Lequang

    IPC分类号： H01R2368

    CPC分类号： H01L22/32 ,  H01L21/4821 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K3/0052 ,  H05K3/242 ,  H05K2203/1545 ,  H05K2203/162 ,  H05K2203/175 ,  Y10T29/49156 ,  H01L2924/00

    摘要： A variety of improved substrate structures and substrate fabrication techniques for use in integrated circuit packaging are described. In one aspect, a substrate strip fabrication technique that facilitates strip testing of the dice mounted thereon is described. The described technique works well even when landings on the substrate are electrolytically plated. In a preferred embodiment, the substrate is formed in a manner that facilitates the use of non-stick detection during wire bonding. In a distinct aspect of the invention the substrate strip has a plurality of distinct molding area tiles that each have a two dimensional array of substrate segments formed thereon. The substrate segments each have a die attach area, a plurality of landing one surface and a plurality of contact pads on the other. The contact pads are positioned substantially across from the landings and are electrically connected thereto by associated vias. The landings have bond pads suitable for use in wire bonding and are preferably arranged in at least one row that extends adjacent or around the die attach area. The contact pads are positioned opposite the landings. With this arrangement, extended routing traces are not required to electrically couple the bond pads to the contact pads.

    摘要翻译： 描述了用于集成电路封装的各种改进的衬底结构和衬底制造技术。 在一个方面，描述了一种便于对安装在其上的裸片进行条带测试的衬底条制造技术。 所描述的技术甚至在基板上的着陆被电镀时也能很好地工作。 在一个优选实施例中，以有助于在引线接合期间使用不粘检测的方式形成衬底。 在本发明的一个明显的方面，衬底条带具有多个不同的成型区域瓦片，每一个都具有形成在其上的衬底段的二维阵列。 基板片段各自具有管芯附着区域，多个着陆一个表面和另一个的多个接触焊盘。 接触垫基本上位于平台的两侧，并通过相关的通孔与其电连接。 着陆具有适合用于引线接合的接合焊盘，并且优选地布置在邻近或围绕芯片附接区域延伸的至少一行中。 接触垫位于与平台相对的位置。 通过这种布置，不需要延长布线迹线来将接合焊盘电耦合到接触焊盘。