公开(公告)号：US06784066B2

公开(公告)日：2004-08-31

申请号：US09960974

申请日：2001-09-25

申请人： Atsushi Hachisuka

发明人： Atsushi Hachisuka

IPC分类号： H01L2120

CPC分类号： H01L27/10894 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823468 ,  H01L27/10873 ,  H01L29/6656

摘要： A plurality of gate electrodes is formed on a semiconductor substrate having a DRAM area and a logic area. Next, sidewalls, each of which includes a silicon nitride film covering the sides of gate electrodes and a silicon oxide film covering the silicon nitride film, are formed on the sides of the gate electrodes respectively. After formation of a transistor having an LDD structure in the logic area, the silicon oxide film formed on the sides of the gate electrodes is removed by wet etching. Next, a silicon nitride film is formed on the whole surface of the semiconductor substrate, and an interlayer dielectric is formed on the silicon nitride film.

摘要翻译： 在具有DRAM区域和逻辑区域的半导体衬底上形成多个栅电极。 接下来，分别在栅电极的侧面分别形成各自包括覆盖栅电极的侧面的氮化硅膜和覆盖氮化硅膜的氧化硅膜的侧壁。 在逻辑区域中形成具有LDD结构的晶体管之后，通过湿蚀刻去除形成在栅电极侧面上的氧化硅膜。 接下来，在半导体衬底的整个表面上形成氮化硅膜，并在氮化硅膜上形成层间电介质。

公开(公告)号：US5892291A

公开(公告)日：1999-04-06

申请号：US670313

申请日：1996-06-27

申请人： Koichiro Narimatsu ,  Shigenori Yamashita ,  Nobuyuki Yoshioka ,  Shinya Soeda ,  Atsushi Hachisuka ,  Koji Taniguchi ,  Yuki Miyamoto ,  Takayuki Saito ,  Ayumi Minamide

发明人： Koichiro Narimatsu ,  Shigenori Yamashita ,  Nobuyuki Yoshioka ,  Shinya Soeda ,  Atsushi Hachisuka ,  Koji Taniguchi ,  Yuki Miyamoto ,  Takayuki Saito ,  Ayumi Minamide

IPC分类号： G03F1/36 ,  G03F1/42 ,  G03F7/20 ,  G03F9/00 ,  H01L21/027 ,  H05K1/02 ,  H01L23/544

CPC分类号： G03F7/706 ,  G03F7/70633 ,  Y10T428/24802 ,  Y10T428/24917

摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.

摘要翻译： 本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件， 以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。 第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案 。 因此，可以提供考虑到像差影响的配准精度测量标记。

公开(公告)号：US5672533A

公开(公告)日：1997-09-30

申请号：US555414

申请日：1995-11-09

申请人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L21/8242 ,  H01L29/68 ,  H01L29/76 ,  H01L29/78 ,  H01L29/92 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L27/1085 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/66659

摘要： Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.

摘要翻译： 公开了一种半导体存储器件，其中可以有效地减少电容器和源极/漏极区域之间的结区中的晶体缺陷和晶体管的短沟道效应。 半导体存储器件包括在电容器连接的栅电极侧，形成为具有比位线侧的侧壁宽度大的侧壁以及源极/漏极区， 电容器被连接并且被形成为具有比相对的源极/漏极区的扩散深度更大的扩散深度。 因此，源极/漏极区域有效地防止在电容器和连接到电容器的源极/漏极区域之间的结区域中产生晶体缺陷，并且侧壁有效地降低了短沟道效应。

公开(公告)号：US5597755A

公开(公告)日：1997-01-28

申请号：US457193

申请日：1995-06-01

申请人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

发明人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10817 ,  H01L27/10852

摘要： A method of manufacturing a semiconductor memory device having stacked capacitors is disclosed. After forming a capacitor isolating layer on an insulation layer and forming a contact hole in the insulation layer, a first conductive layer is formed on the insulating layer and the capacitor isolating layer and on an inner surface of the contact hole. The first conductive layer is partially etched and removed by using an etch-back technique to be isolated into a first capacitor portion and a second capacitor portion. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer.

摘要翻译： 公开了一种制造具有层叠电容器的半导体存储器件的方法。 在绝缘层上形成电容器隔离层并在绝缘层中形成接触孔之后，在绝缘层和电容器隔离层上以及接触孔的内表面上形成第一导电层。 通过使用蚀刻技术将第一导电层部分地蚀刻和去除，以将其隔离成第一电容器部分和第二电容器部分。 在第一导电层上形成电介质层。 在介电层上形成第二导电层。

公开(公告)号：US5578861A

公开(公告)日：1996-11-26

申请号：US357298

申请日：1994-12-13

申请人： Mitsuya Kinoshita ,  Atsushi Hachisuka ,  Kazuhiro Tsukamoto

发明人： Mitsuya Kinoshita ,  Atsushi Hachisuka ,  Kazuhiro Tsukamoto

IPC分类号： H01L27/04 ,  H01L21/82 ,  H01L21/822 ,  H01L23/525 ,  H01L27/10 ,  H01L23/62 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002

摘要： In a semiconductor device, a connection conductive layer is formed by patterning on a p-type semiconductor substrate. A silicon nitride film is formed on the connection conductive layer with an insulating layer. A silicon oxide film is formed on the silicon nitride film. The silicon oxide film is provided with a hole. The silicon nitride film is exposed at a bottom of the hole. The hole is located immediately above the connection conductive layer. Thereby, a thickness of the insulating layer on a fuse element which can be blown can be controlled easily in the semiconductor device.

摘要翻译： 在半导体器件中，通过在p型半导体衬底上图案化形成连接导电层。 在具有绝缘层的连接导电层上形成氮化硅膜。 在氮化硅膜上形成氧化硅膜。 氧化硅膜设置有孔。 氮化硅膜暴露在孔的底部。 孔位于连接导电层的正上方。 由此，可以在半导体器件中容易地控制能够熔断的熔丝元件上的绝缘层的厚度。

公开(公告)号：US5448512A

公开(公告)日：1995-09-05

申请号：US44676

申请日：1993-04-09

申请人： Atsushi Hachisuka ,  Kazuhiro Tsukamoto ,  Mitsuya Kinoshita

发明人： Atsushi Hachisuka ,  Kazuhiro Tsukamoto ,  Mitsuya Kinoshita

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  G11C11/401

CPC分类号： H01L27/10817

摘要： A portion of a cell plate 91 extending upon a field oxide film 107a and a silicon oxide film 123 is referred to as a lower layer interconnection film 109. The lower layer interconnection film 109 has a concave shape. A through hole 95a is formed in a silicon oxide film 93 reaching the bottom of the concave shape lower layer interconnection film 109. The depth of the through hole 95a is greater in comparison with the case where a through hole is formed on an upper face portion 123a of the silicon oxide film 123. Because the depth of through hole 95a is great, the thickness of the tungsten film 101a formed in through hole 95a becomes thicker. This eliminates the problem that all the tungsten film 101a in the through hole 95a, and then a portion of the lower layer interconnection film 109 are overetched. Therefore, electrical connection between the upper layer interconnection layer 103a and the lower layer interconnection layer 109 can be ensured.

摘要翻译： 在场氧化膜107a和氧化硅膜123上延伸的单元板91的一部分被称为下层互连膜109.下层布线膜109具有凹形。 在到达凹形下层互连膜109的底部的氧化硅膜93中形成通孔95a。与在上表面部分形成通孔的情况相比，通孔95a的深度更大 123a。由于通孔95a的深度大，所以形成在通孔95a中的钨膜101a的厚度变厚。 这消除了通孔95a中的所有钨膜101a以及下层互连膜109的一部分被过蚀刻的问题。 因此，可以确保上层布线层103a和下层布线层109之间的电连接。

公开(公告)号：US08072074B2

公开(公告)日：2011-12-06

申请号：US12975004

申请日：2010-12-21

申请人： Atsushi Hachisuka ,  Atsushi Amo ,  Tatsuo Kasaoka ,  Shunji Kubo

发明人： Atsushi Hachisuka ,  Atsushi Amo ,  Tatsuo Kasaoka ,  Shunji Kubo

IPC分类号： H01L23/48

CPC分类号： H01L27/10829 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/485 ,  H01L27/10811 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).

公开(公告)号：US06388295B1

公开(公告)日：2002-05-14

申请号：US09663717

申请日：2000-09-18

申请人： Tomohiro Yamashita ,  Yoshinori Okumura ,  Atsushi Hachisuka ,  Shinya Soeda

发明人： Tomohiro Yamashita ,  Yoshinori Okumura ,  Atsushi Hachisuka ,  Shinya Soeda

IPC分类号： H01L2976

CPC分类号： H01L21/823493 ,  H01L21/761 ,  H01L27/10897

摘要： The semiconductor device has a triple well structure. The triple well and other wells have impurity concentration distributions in the depth direction, which are determined in accordance with required function. Thereby, the required performances such as suppression of a leak current can be achieved even in a miniaturized structure.

摘要翻译： 半导体器件具有三重阱结构。 三井等井在深度方向具有杂质浓度分布，根据所需的功能确定。 因此，即使在小型化结构中也能够实现抑制漏电流等所需的性能。

公开(公告)号：US06218235B1

公开(公告)日：2001-04-17

申请号：US09542876

申请日：2000-04-04

申请人： Atsushi Hachisuka ,  Hiroyasu Nohsoh ,  Shinya Soeda

发明人： Atsushi Hachisuka ,  Hiroyasu Nohsoh ,  Shinya Soeda

IPC分类号： H01L218242

CPC分类号： H01L27/10873 ,  H01L27/10894

摘要： A method of manufacturing a semiconductor device having a memory device and a logic device on the same semiconductor substrate is provided without reducing reliability of the semiconductor device and making a manufacturing process unnecessarily complicated. A silicon oxide film which serves as a salicide protection film in the logic device formation region is subjected to wet isotropic etching. The process completely removes the silicon oxide film in the memory device formation region. Thus, the silicon oxide film is left only in a prescribed portion in the logic device formation region. As a result, the silicon oxide film is not left on an inner wall of a recess formed by a silicon nitride film between gate electrodes. Consequently, a good self alignment contact opening is formed toward a source/drain region in the memory device formation region.

摘要翻译： 在不降低半导体器件的可靠性并使制造工艺不必要地复杂的情况下，提供具有在同一半导体衬底上的存储器件和逻辑器件的半导体器件的制造方法。 在逻辑器件形成区域中用作硅化物保护膜的氧化硅膜经受湿均匀蚀刻。 该过程完全去除存储器件形成区域中的氧化硅膜。 因此，氧化硅膜仅留在逻辑器件形成区域中的规定部分。 结果，氧化硅膜不留在由栅电极之间的氮化硅膜形成的凹部的内壁上。 因此，存储器件形成区域中的源极/漏极区域形成良好的自对准接触开口。

公开(公告)号：US6160284A

公开(公告)日：2000-12-12

申请号：US687934

申请日：1996-07-29

申请人： Atsushi Hachisuka ,  Takeshi Noguchi

发明人： Atsushi Hachisuka ,  Takeshi Noguchi

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L21/76805 ,  H01L21/76831 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885

摘要： Source/drain regions of an MOS transistor are formed at a surface of a p-type silicon substrate. A storage node electrically connected to the source/drain regions penetrates a bit line to reach the n-type source/drain region. The storage node and the bit line are insulated from each other by a sidewall insulating layer. Thus, a semiconductor memory device suitable for high integration is obtained in which short-circuit between the storage node and the bit line on a gate electrode layer can be prevented.

摘要翻译： 在p型硅衬底的表面上形成MOS晶体管的源极/漏极区域。 电连接到源极/漏极区域的存储节点穿过位线以到达n型源极/漏极区域。 存储节点和位线通过侧壁绝缘层彼此绝缘。 因此，可以获得适于高集成度的半导体存储器件，其中可以防止存储节点和栅极电极层上的位线之间的短路。