Abstract:
A system and method for using an embedded microprocessor in an RF amplifier. The use of an embedded microprocessor avoids manual calibration. The Microprocessor collects initial amplifier performance data based on a set of parameters and calculates the needed corrections. The microprocessor can change levels within the circuit to achieve those operating points. The embedded microprocessor sets voltage levels with internal circuitry and communicates this information externally through a serial communication port, or the like, to allow a user to communicate with and look at the amplifier data and readjust the internal bias levels, as needed. Thus, the internal microprocessor provides for calibration, self-testing, and monitoring of the RF amplifier and also functions as an in situ bias and temperature compensation controller for use in the presence of temperature variation and provides bias sequencing control to protect against improper applied timing of voltage inputs to the amplifier.
Abstract:
A solid-state amplifier architecture is disclosed. In some embodiments, the disclosed architecture may include first and second channel chipsets configured to amplify either the entire instantaneous frequency band of a radio frequency (RF) input signal or, respectively, sub-bands thereof, which may be divided proportionally between the two chipsets. In some cases, the chipsets may be configured to amplify frequencies in excess of the entire K-band and Ka-band frequencies simultaneously. In some cases, the architecture may be configured to address a signal received, for instance, from an electronic warfare (EW) system to a log amplifier stage configured to output a signal to the EW system, in response to which the EW system may generate a RF signal for amplification by the architecture for transmission. To facilitate heat dissipation, the architecture may be coupled, in part or in whole, with a thermally conductive carrier, optionally with an intervening diamond heat spreader layer.
Abstract:
Techniques and architecture are disclosed for providing an ultra-wideband, multi-channel solid-state power amplifier architecture. In some embodiments, the architecture includes a power divider which splits an input signal and delivers that split signal to a plurality of downstream channel chipsets. Each channel chipset is configured to amplify a sub-band of the original full-band input signal and to provide the resultant amplified sub-band for downstream use, such as for transmission by an antenna operatively coupled with that channel. In the aggregate, the amplified sub-bands provide coverage of the same ultra-wideband frequency range of the original input signal, in some cases. In some embodiments, the architecture provides high radio frequency (RF) power with good amplifying efficiency and ultra-wide instantaneous frequency bandwidth performance in a small-form-factor package. In some instances, control circuitry is provided to control which chipset die(s) are enabled/disabled, thus providing control over gain and power levels of the output signal(s).
Abstract:
In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.
Abstract:
An ultra-wideband high-power solid-state transmitter for electronic warfare applications which includes a plurality of wideband Gallium-Nitride (GaN) semiconductor monolithic-microwave integrated circuits (MMICs), a spatial power combiner to sum the aggregate contribution of the MMICs, a wide bandwidth small form factor driver amplifier module to supply the required gain in the transmitter, and a thermal management system.
Abstract:
Techniques and architecture are disclosed for providing an ultra-wideband, multi-channel solid-state power amplifier architecture. In some embodiments, the architecture includes a power divider which splits an input signal and delivers that split signal to a plurality of downstream channel chipsets. Each channel chipset is configured to amplify a sub-band of the original full-band input signal and to provide the resultant amplified sub-band for downstream use, such as for transmission by an antenna operatively coupled with that channel. In the aggregate, the amplified sub-bands provide coverage of the same ultra-wideband frequency range of the original input signal, in some cases. In some embodiments, the architecture provides high radio frequency (RF) power with good amplifying efficiency and ultra-wide instantaneous frequency bandwidth performance in a small-form-factor package. In some instances, control circuitry is provided to control which chipset die(s) are enabled/disabled, thus providing control over gain and power levels of the output signal(s).