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    LDMOS One-Time Programmable Device
    1.
    发明申请
    LDMOS One-Time Programmable Device 有权
    LDMOS一次性可编程器件

    公开(公告)号：US20130299904A1

    公开(公告)日：2013-11-14

    申请号：US13945739

    申请日：2013-07-18

    Applicant: Broadcom Corporation

    Inventor： Akira Ito ,  Xiangdong Chen

    IPC: H01L29/78 ,  H01L27/088

    CPC classification number: H01L29/7816 ,  H01L21/76224 ,  H01L23/5252 ,  H01L27/088 ,  H01L27/11206 ,  H01L27/11226 ,  H01L27/1124 ,  H01L27/11246 ,  H01L27/11266 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

    Abstract translation: 根据一个实施例，具有横向扩散的金属氧化物半导体（LDMOS）结构的一次性可编程（OTP）器件包括包括通过栅极电极和通过栅极电介质的通过栅极，以及包括编程门 电极和编程栅极电介质。 编程门通过LDMOS结构的漏极扩展区与通过栅极间隔开。 当用于将编程栅极电介质破裂的编程电压施加到编程栅电极时，LDMOS结构为通路提供保护。 一种用于制造这种OTP器件的方法包括形成漏极延伸区域，在漏极延伸区域的第一部分上制造栅极通孔，以及在漏极延伸区域的第二部分上制造编程栅极。

    LDMOS one-time programmable device
    3.
    发明授权
    LDMOS one-time programmable device 有权
    LDMOS一次性可编程器件

    公开(公告)号：US08969957B2

    公开(公告)日：2015-03-03

    申请号：US13945739

    申请日：2013-07-18

    Applicant: Broadcom Corporation

    Inventor： Akira Ito ,  Xiangdong Chen

    IPC: H01L21/70 ,  H01L23/52 ,  H01L29/78 ,  H01L27/112 ,  H01L23/525 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L29/51

    CPC classification number: H01L29/7816 ,  H01L21/76224 ,  H01L23/5252 ,  H01L27/088 ,  H01L27/11206 ,  H01L27/11226 ,  H01L27/1124 ,  H01L27/11246 ,  H01L27/11266 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

    Abstract translation: 根据一个实施例，具有横向扩散的金属氧化物半导体（LDMOS）结构的一次性可编程（OTP）器件包括包括通过栅极电极和通过栅极电介质的通过栅极，以及包括编程门 电极和编程栅极电介质。 编程门通过LDMOS结构的漏极扩展区与通过栅极间隔开。 当用于将编程栅极电介质破裂的编程电压施加到编程栅电极时，LDMOS结构为通路提供保护。 一种用于制造这种OTP器件的方法包括形成漏极延伸区域，在漏极延伸区域的第一部分上制造栅极通孔，以及在漏极延伸区域的第二部分上制造编程栅极。

    FinFET based one-time programmable device
    4.
    发明授权
    FinFET based one-time programmable device 有权
    FinFET一次性可编程器件

    公开(公告)号：US08923070B2

    公开(公告)日：2014-12-30

    申请号：US14063440

    申请日：2013-10-25

    Applicant: Broadcom Corporation

    Inventor： Wei Xia ,  Xiangdong Chen

    IPC: G11C11/34 ,  H01L29/78 ,  H01L27/112 ,  G11C17/12 ,  H01L23/525

    CPC classification number: H01L29/7855 ,  G11C11/34 ,  G11C17/12 ,  H01L23/5252 ,  H01L27/11206 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one embodiment, a one-time programmable (OTP) device comprises a memory FinFET in parallel with a sensing FinFET. The memory FinFET and the sensing FinFET share a common source region, a common drain region, and a common channel region. The memory FinFET is programmed by having a ruptured gate dielectric, resulting in the sensing FinFET having an altered threshold voltage and an altered drain current. A method for utilizing such an OTP device comprises applying a programming voltage for rupturing the gate dielectric of the memory FinFET thereby achieving a programmed state of the memory FinFET, and detecting by the sensing FinFET the altered threshold voltage and the altered drain current due to the programmed state of the memory FinFET.

    Abstract translation: 根据一个实施例，一次性可编程（OTP）器件包括与感测FinFET并联的存储器FinFET。 存储器FinFET和感测FinFET共享共源极区，公共漏极区和公共沟道区。 存储器FinFET通过具有破裂的栅极电介质来编程，导致感测FinFET具有改变的阈值电压和改变的漏极电流。 一种利用这种OTP器件的方法包括施加用于破坏存储器FinFET的栅极电介质的编程电压，从而实现存储器FinFET的编程状态，并且通过感测FinFET检测改变的阈值电压和改变的漏极电流，由于 存储器FinFET的编程状态。

    Method of fabricating a flash memory comprising a high-K dielectric and a metal gate
    5.
    发明授权
    Method of fabricating a flash memory comprising a high-K dielectric and a metal gate 有权
    制造包括高K电介质和金属栅极的闪速存储器的方法

    公开(公告)号：US08822286B2

    公开(公告)日：2014-09-02

    申请号：US14050748

    申请日：2013-10-10

    Applicant: Broadcom Corporation

    Inventor： Wei Xia ,  Xiangdong Chen ,  Frank Hui

    IPC: H01L21/336

    CPC classification number: H01L21/28273 ,  H01L27/11526 ,  H01L27/11546

    Abstract: According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric o one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

    Abstract translation: 根据一个示例性实施例，一种用于在半导体管芯中制造快闪存储器单元的方法包括：在衬底的存储器区域中形成覆盖浮置栅极堆叠的控制栅极堆叠，其中浮置栅极堆叠包括覆盖一部分 电介质层。 浮栅包括金属一层的一部分，电介质层包括第一高k电介质材料。 控制栅极堆叠可以包括包括金属两层的一部分的控制栅极，其中金属一层可以包括与金属两层不同的金属。

    Zener Diode Structure and Process
    6.
    发明申请
    Zener Diode Structure and Process 有权
    齐纳二极管结构与工艺

    公开(公告)号：US20130288439A1

    公开(公告)日：2013-10-31

    申请号：US13924115

    申请日：2013-06-21

    Applicant: Broadcom Corporation

    Inventor： Wei XIA ,  Xiangdong Chen

    IPC: H01L21/8238

    CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L24/13 ,  H01L24/14 ,  H01L27/0629 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2924/12035 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

    Abstract: A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

    Abstract translation: 垂直堆叠的平面结齐纳二极管与外延生长的FET升高的S / D端子同时形成。 齐纳二极管的结构和工艺与Gate-Last高k FET结构和工艺兼容。 二极管和晶体管结构的横向分离由改进的STI屏蔽提供。 不需要额外的光刻步骤。 在一些实施例中，最上面的二极管端子的非结面用镍硅化，以另外作为铜扩散阻挡层。

    Zener diode structure and process
    9.
    发明授权
    Zener diode structure and process 有权
    齐纳二极管结构和工艺

    公开(公告)号：US08993392B2

    公开(公告)日：2015-03-31

    申请号：US13924115

    申请日：2013-06-21

    Applicant: Broadcom Corporation

    Inventor： Wei Xia ,  Xiangdong Chen

    IPC: H01L21/8238 ,  H01L27/06 ,  H01L23/00

    CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L24/13 ,  H01L24/14 ,  H01L27/0629 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2924/12035 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

    Abstract: A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

    Abstract translation: 垂直堆叠的平面结齐纳二极管与外延生长的FET升高的S / D端子同时形成。 齐纳二极管的结构和工艺与Gate-Last高k FET结构和工艺兼容。 二极管和晶体管结构的横向分离由改进的STI屏蔽提供。 不需要额外的光刻步骤。 在一些实施例中，最上面的二极管端子的非结面用镍硅化，以另外作为铜扩散阻挡层。

    Decoupling composite capacitor in a semiconductor wafer
    10.
    发明授权
    Decoupling composite capacitor in a semiconductor wafer 有权
    在半导体晶片中去耦合复合电容器

    公开(公告)号：US08883605B2

    公开(公告)日：2014-11-11

    申请号：US13952201

    申请日：2013-07-26

    Applicant: Broadcom Corporation

    Inventor： Xiangdong Chen ,  Wei Xia

    IPC: H01L49/02 ,  H01L29/94

    CPC classification number: H01L28/40 ,  H01L28/90 ,  H01L29/94 ,  H01L29/945

    Abstract: According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode.

    Abstract translation: 根据示例性实施例，在晶片中制造去耦复合电容器的方法包括覆盖在衬底上的电介质区域包括在电介质区域和衬底中形成贯通晶片通孔。 贯通晶片通孔包括覆盖贯通晶片通孔开口的侧壁和底部的贯通晶片通孔绝缘体，以及通过绝缘体覆盖贯通晶片的贯通晶片通孔导体。 该方法还包括使衬底变薄，形成衬底背面绝缘体，在衬底背面绝缘体中形成开口以通过导体暴露通过晶片，以及通过导体在透晶片上形成背面导体，使得衬底背侧导体 延伸到衬底背面绝缘体上，从而形成去耦复合电容器。 衬底形成第一去耦合复合电容器电极，并且通过晶片通孔导体和衬底背侧导体形成第二去耦复合电容器电极。

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