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    Capacitive mounting arrangement for securing an integrated circuit package to a heat sink
    3.
    发明授权
    Capacitive mounting arrangement for securing an integrated circuit package to a heat sink 失效
    用于将集成电路封装固定到散热器的电容安装布置

    公开(公告)号：US06160710A

    公开(公告)日：2000-12-12

    申请号：US054972

    申请日：1998-04-03

    申请人： Bengt Ahl ,  Larry C. Leighton ,  Thomas W. Moller

    发明人： Bengt Ahl ,  Larry C. Leighton ,  Thomas W. Moller

    IPC分类号： H01L23/40 ,  H05K1/02 ,  H05K1/18 ,  H05K3/32 ,  H05K7/20

    CPC分类号： H01L23/4006 ,  H01L2023/4031 ,  H01L2023/405 ,  H01L2023/4062 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/0243 ,  H05K1/182 ,  H05K3/325 ,  H05K2201/10166 ,  H05K2201/10409 ,  H05K2201/10416 ,  H01L2924/00

    摘要： A thermally conductive mounting flange of an IC package is placed directly on a heat sink surface between respective sections of single layer PC board attached to the heat sink, such that electrical leads extending from opposing sides of the package are positioned over corresponding conductive areas formed on the surface of the respective adjacent PC board section. The leads are electrically coupled with the conductive areas by respective tie-down screws fastened through dielectric isolating washers. The screws are tightened sufficiently against the isolating washers so as to press the respective package leads into solid electrical contact with the conductive areas. Portions of the respective leads and conductive areas surrounding the tie-down screws are cut-away to prevent electrical contact, in order to avoid shorting the leads and/or conductive areas to the heat sink via the tie-down screws. Alternately, respective ends of a retaining spring used to secure the IC package to the heat sink mounting flange are also secured by the package lead tie-down screws, such that the screws both secure the package against the heat sink and press the package leads into solid electrical contact with the respective conductive areas.

    摘要翻译： IC封装的导热安装凸缘直接放置在连接到散热器的单层PC板的相应部分之间的散热器表面上，使得从封装的相对侧延伸的电引线定位在形成于 相邻PC板部分的表面。 引线通过通过介电隔离垫圈固定的相应的固定螺丝与导电区域电耦合。 螺钉被紧固到隔离垫圈上，以将相应的包装引线按压到与导电区域的固体电接触。 相应的引线和围绕固定螺钉的导电区域的部分被切除以防止电接触，以避免通过固定螺钉将引线和/或导电区域短路到散热器。 或者，用于将IC封装固定到散热器安装凸缘的固定弹簧的相应端部也通过封装引线固定螺钉固定，使得螺钉将封装固定在散热器上并将封装引线压入 与相应的导电区域固体电接触。

    Mounting arrangement for securing an intergrated circuit package to heat sink
    4.
    发明授权
    Mounting arrangement for securing an intergrated circuit package to heat sink 失效
    将集成电路封装固定在散热片上的安装方式

    公开(公告)号：US5869897A

    公开(公告)日：1999-02-09

    申请号：US956193

    申请日：1997-10-22

    申请人： Larry C. Leighton ,  Thomas W. Moller ,  Bengt Ahl

    发明人： Larry C. Leighton ,  Thomas W. Moller ,  Bengt Ahl

    IPC分类号： H01L23/40 ,  H05K7/00 ,  H01L23/00 ,  H05K7/20

    CPC分类号： H01L23/40 ,  H01L2924/0002

    摘要： A top surface of a protective cover of an IC component package is provided with a centered-protrusion, e.g., such as a cylindrical peg, that extends above the cover. A retaining-spring is formed by twisting a resilient (e.g., metal) metal strip into a ribbon-like shape having opposing ends that extend from a curvelinear bottom surface. The bottom surface of the retaining-spring is provided with an opening configured to mate with the centered protrusion on the package cover, such that the opposing ends of the retaining-spring extend away from the package cover at substantially the same, albeit reverse angles. In order to mount the IC package to a heat sink, the bottom surface of the retaining-spring may be compressively mated onto the package cover at the same time the package is inserted between two substantially parallel walls protruding from the heat sink surface, wherein the walls are distanced from each other. just so as to cause moderate compression of the opposing ends of the spring toward each other as the package is inserted against the heat sink surface. The opposing surfaces of the two walls are provided with a plurality of notches formed substantially parallel to the heat sink surface in a "ratchet-type" relief pattern, such that the opposing ends of the retaining-spring are held into place by respective notches, once the IC package is secured against the heat sink.

    摘要翻译： IC组件封装的保护盖的顶表面设置有在盖上延伸的中心突起，例如圆柱形钉。 通过将弹性（例如，金属）金属条扭转成具有相对端部的带状形状来形成保持弹簧，所述相对端部从光栅底表面延伸。 保持弹簧的底表面设置有开口，该开口构造成与包装盖上的中心突出部配合，使得保持弹簧的相对端部基本上以相反的角度延伸离开包装盖。 为了将IC封装安装到散热器，保持弹簧的底表面可以压缩地配合到封装盖上，同时将封装插入从散热器表面突出的两个基本平行的壁之间，其中 墙壁彼此远离。 只是当包装被插入散热器表面时，使弹簧的相对端部彼此相应地适度地压缩。 两个壁的相对表面设置有以“棘轮型”浮雕图案基本上平行于散热器表面形成的多个凹口，使得保持弹簧的相对端部通过相应的凹口保持就位， 一旦IC封装固定在散热片上。

    Resistive interconnect of transistor cells
    6.
    发明授权
    Resistive interconnect of transistor cells 失效
    晶体管单元的电阻互连

    公开(公告)号：US5982000A

    公开(公告)日：1999-11-09

    申请号：US055023

    申请日：1998-04-03

    申请人： Larry C. Leighton ,  Thomas W. Moller ,  Nils af Ekenstam ,  Jan Johansson

    发明人： Larry C. Leighton ,  Thomas W. Moller ,  Nils af Ekenstam ,  Jan Johansson

    IPC分类号： H01L23/482 ,  H01L29/78

    CPC分类号： H01L23/4824 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： A plurality of transistor cells (36) formed on a semiconductor substrate (32) are connected to form a radio frequency power transistor device (30), whereby individual conductive paths (38) are formed on one side of the substrate (32) to connect respective common gate terminals (34) of adjacent transistor cells (36) in series. A further conductive path (40) is formed on an opposite side of the substrate connecting respective drain terminals (35) of the transistor cells (36) in parallel. A resistive element (42) is interposed in the conductive path (38) connecting each adjacent pair of gate terminals (34). The conductivity of the respective resistive elements (42) is selected so as to adequately provide a conductive pathway for connecting the respective gate terminal outputs, while being sufficiently resistive such that each gate terminal 34 "sees" an electrical circuit termination.

    摘要翻译： 形成在半导体衬底（32）上的多个晶体管单元（36）被连接以形成射频功率晶体管器件（30），由此在衬底（32）的一侧上形成各个导电通路（38）以连接 相邻晶体管单元（36）的各个公共栅极端子（34）串联。 另外的导电路径（40）形成在与晶体管单元（36）的各个漏极端子（35）并联连接的衬底的相对侧。 电阻元件（42）被插入连接每个相邻的一对栅极端子（34）的导电路径（38）中。 选择各个电阻元件（42）的导电性，以便充分地提供用于连接各个栅极端子输出的导电路径，同时具有足够的电阻性，使得每个栅极端子34“看到”电路端接。

    Multi-stage, high frequency, high power signal amplifier
    7.
    发明授权
    Multi-stage, high frequency, high power signal amplifier 有权
    多级，高频，高功率信号放大器

    公开(公告)号：US06614308B2

    公开(公告)日：2003-09-02

    申请号：US10037638

    申请日：2001-10-22

    申请人： Thomas W. Moller ,  Larry Leighton ,  Prasanth Perugupalli

    发明人： Thomas W. Moller ,  Larry Leighton ,  Prasanth Perugupalli

    IPC分类号： H03F368

    CPC分类号： H01L24/49 ,  H01L23/48 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6644 ,  H01L2223/665 ,  H01L2224/32188 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/1306 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H03F3/604 ,  H01L2924/00 ,  H01L2224/45099

    摘要： A broadband RF signal amplifier includes a plurality of transistors attached to a surface of a pedestal, each transistor having an input and an output. An RF input path electrically connected to the transistor inputs includes a passive splitter implemented in a multi-layer printed circuit board and configured to split a RF input signal into a plurality of component input signals. A plurality of corresponding input matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple respective component input signals to the transistor inputs at an input impedance, the input matching networks further comprising respective input matching capacitors attached to the pedestal. An RF output path electrically connected to the transistor outputs includes a passive combiner implemented in the printed circuit board and configured to combine component output signals received at the transistor outputs into a RF output signal. A plurality of corresponding output matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple the respective component output signals at the transistor outputs to an output impedance.

    摘要翻译： 宽带RF信号放大器包括附接到基座的表面的多个晶体管，每个晶体管具有输入和输出。 电连接到晶体管输入的RF输入路径包括实现在多层印刷电路板中并被配置为将RF输入信号分成多个分量输入信号的无源分离器。 包括在印刷电路板中实现的四分之一波长传输线的多个对应的输入匹配网络将各个分量输入信号以输入阻抗耦合到晶体管输入，输入匹配网络还包括附接到基座的相应的输入匹配电容器。 电连接到晶体管输出的RF输出路径包括在印刷电路板中实现的被配置以将在晶体管输出处接收的分量输出信号组合成RF输出信号的无源组合器。 包括在印刷电路板中实施的四分之一波长传输线的多个对应的输出匹配网络将晶体管输出端处的各个分量输出信号耦合到输出阻抗。

    RF power package with a dual ground
    8.
    发明授权
    RF power package with a dual ground 失效
    射频功率封装带双地

    公开(公告)号：US5889319A

    公开(公告)日：1999-03-30

    申请号：US684474

    申请日：1996-07-19

    申请人： Thomas W. Moller ,  Larry Leighton

    发明人： Thomas W. Moller ,  Larry Leighton

    IPC分类号： H01L23/12 ,  H01L23/66 ,  H01L23/52

    CPC分类号： H01L23/66 ,  H01L2223/6644 ,  H01L2924/0002

    摘要： An RF power transistor package is configured for mounting to a heat sink in a multi-layer pc board, and includes a direct top side electrical ground path from a transistor chip located atop a ceramic substrate to a mounting flange, without passing through the ceramic substrate by way of metal plating an outer surface of the ceramic substrate to electrically connect a top mounted metal lead to the flange. A direct ground path from the transistor chip to the mounting flange is also provided by way of plated via holes through the ceramic substrate. The top side ground path is also configured to connect with the middle ground reference layer of the multi-layer pc board when the mounting flange is secured to the heat sink, so that a unified ground potential is seen by the transistor at both the middle layer and heat sink. In this manner, the power transistor package is grounded at the same reference potential as other elements attached to the pc board, while still having the high performance characteristics provided by the ground path via holes.

    摘要翻译： RF功率晶体管封装被配置为安装到多层印刷电路板中的散热器，并且包括从位于陶瓷基板顶部到安装凸缘的晶体管芯片的直接顶侧电接地路径，而不通过陶瓷基板 通过金属电镀陶瓷基板的外表面以将顶部安装的金属引线电连接到凸缘。 从晶体管芯片到安装法兰的直接接地路径也通过穿过陶瓷基板的电镀通孔提供。 当安装法兰固定在散热片上时，顶面接地路径也可以与多层印刷电路板的中间参考层连接，从而在晶体管的中间层看到统一的接地电位 和散热器。 以这种方式，功率晶体管封装以与附接到印刷电路板的其它元件相同的参考电位接地，同时仍具有由接地路径通孔提供的高性能特性。

    Liquid dielectric tuning of an integrated circuit
    9.
    发明授权
    Liquid dielectric tuning of an integrated circuit 失效
    集成电路的液体介质调谐

    公开(公告)号：US06515235B2

    公开(公告)日：2003-02-04

    申请号：US09871374

    申请日：2001-05-30

    申请人： Thomas W. Moller

    发明人： Thomas W. Moller

    IPC分类号： H05K109

    CPC分类号： H05K1/0272 ,  H01P1/184 ,  H01P9/00

    摘要： A desired performance characteristic of an electrical circuit employing a strip conductor is achieved by placing a fluid having a selected dielectric property in contact with at least a portion of the strip conductor, such that the dielectric property of the fluid effects one or more transmission characteristics of the conductor. In one embodiment, the circuit performance is measured and the dielectric property of the fluid adjusted, e.g., in an iterative process, until the desired performance characteristic of the circuit is achieved.

    摘要翻译： 使用带状导体的电路的期望的性能特征是通过将具有选定介电性质的流体放置在与带状导体的至少一部分接触的方式实现的，使得流体的介电性能实现一个或多个传输特性 导体。 在一个实施例中，测量电路性能，并且例如在迭代过程中调节的流体的介电性能直到达到电路的期望性能特性。