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    Method for Producing a Semiconductor Device
    2.
    发明申请
    Method for Producing a Semiconductor Device 有权
    制造半导体器件的方法

    公开(公告)号：US20120289023A1

    公开(公告)日：2012-11-15

    申请号：US13365774

    申请日：2012-02-03

    申请人： Carsten Ahrens ,  Rudolf Berger ,  Manfred Frank ,  Uwe Hoeckele ,  Bernhard Knott ,  Ulrich Krumbein ,  Wolfgang Lehnert ,  Berthold Schuderer ,  Juergen Wagner ,  Stefan Willkofer

    发明人： Carsten Ahrens ,  Rudolf Berger ,  Manfred Frank ,  Uwe Hoeckele ,  Bernhard Knott ,  Ulrich Krumbein ,  Wolfgang Lehnert ,  Berthold Schuderer ,  Juergen Wagner ,  Stefan Willkofer

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224 ,  H01L21/762 ,  H01L21/76232 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3185 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench.

    摘要翻译： 一种制造具有侧壁绝缘体的半导体器件的方法包括提供具有第一侧和与第一侧相对的第二侧的半导体本体。 至少一个第一沟槽至少部分地填充有绝缘材料，该绝缘材料从朝向第二侧的方向的第一侧进入半导体本体。 在第一半导体器件的第一半导体体区域和第二半导体器件的第二半导体本体区域之间产生至少一个第一沟槽。 隔离沟槽从半导体本体的第一侧沿第一和第二半导体主体区域之间的半导体本体的第二侧的方向延伸，使得第一沟槽的绝缘材料的至少一部分至少邻接 隔离沟槽的侧壁。 半导体主体的第二面部分地被去除到隔离沟槽的一侧。

    Metallization for Chip Scale Packages in Wafer Level Packaging
    4.
    发明申请
    Metallization for Chip Scale Packages in Wafer Level Packaging 有权
    晶圆级封装芯片尺寸封装的金属化

    公开(公告)号：US20120034760A1

    公开(公告)日：2012-02-09

    申请号：US12851292

    申请日：2010-08-05

    申请人： Berthold Schuderer ,  Carsten Ahrens

    发明人： Berthold Schuderer ,  Carsten Ahrens

    IPC分类号： H01L21/78

    CPC分类号： H01L21/78 ,  H01L2224/02371

    摘要： In one embodiment, a method for forming the semiconductor device includes forming a first trench from a front side of a substrate. The substrate has a front side and an opposite back side, and the first trench having sidewalls and a bottom surface. A insulator layer is formed over the sidewalls and the bottom surface. A first conductive layer is formed over a top portion of the sidewalls of the first trench. The substrate is separated along the first trench.

    摘要翻译： 在一个实施例中，用于形成半导体器件的方法包括从衬底的前侧形成第一沟槽。 衬底具有前侧和相对的后侧，并且第一沟槽具有侧壁和底表面。 在侧壁和底表面上形成绝缘体层。 第一导电层形成在第一沟槽的侧壁的顶部上方。 衬底沿着第一沟槽分离。

    Metallization for chip scale packages in wafer level packaging
    5.
    发明授权
    Metallization for chip scale packages in wafer level packaging 有权
    晶圆级封装中芯片级封装的金属化

    公开(公告)号：US08163629B2

    公开(公告)日：2012-04-24

    申请号：US12851292

    申请日：2010-08-05

    申请人： Berthold Schuderer ,  Carsten Ahrens

    发明人： Berthold Schuderer ,  Carsten Ahrens

    IPC分类号： H01L21/301

    CPC分类号： H01L21/78 ,  H01L2224/02371

    摘要： In one embodiment, a method for forming the semiconductor device includes forming a first trench from a front side of a substrate. The substrate has a front side and an opposite back side, and the first trench having sidewalls and a bottom surface. A insulator layer is formed over the sidewalls and the bottom surface. A first conductive layer is formed over a top portion of the sidewalls of the first trench. The substrate is separated along the first trench.

    摘要翻译： 在一个实施例中，用于形成半导体器件的方法包括从衬底的前侧形成第一沟槽。 衬底具有前侧和相对的后侧，并且第一沟槽具有侧壁和底表面。 在侧壁和底表面上形成绝缘体层。 第一导电层形成在第一沟槽的侧壁的顶部上方。 衬底沿着第一沟槽分离。

    Protective structure having a semiconductor substrate
    10.
    发明授权
    Protective structure having a semiconductor substrate 有权
    具有半导体衬底的保护结构

    公开(公告)号：US08531011B2

    公开(公告)日：2013-09-10

    申请号：US13566039

    申请日：2012-08-03

    申请人： Andre Schmenn ,  Damian Sojka ,  Carsten Ahrens

    发明人： Andre Schmenn ,  Damian Sojka ,  Carsten Ahrens

    IPC分类号： H01L31/075 ,  H01L31/105 ,  H01L31/117

    CPC分类号： H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L29/66121 ,  H01L29/868

    摘要： A protective structure is produced by providing a semiconductor substrate having doping of a first conductivity type. A semiconductor layer having doping of a second conductivity type is applied at a surface of the semiconductor substrate. A buried layer with doping of a second conductivity type is formed in a first region of the semiconductor layer, producing a layer at the junction between the semiconductor layer and semiconductor substrate. A first dopant zone having doping of a first conductivity type is formed in the first region of the semiconductor layer above the buried layer. A second dopant zone having doping of a second conductivity type is formed in a second region of the semiconductor layer. An electrical insulation is formed between the first and second regions of the semiconductor layer. A common connection device is formed for the first and second dopant zones.

    摘要翻译： 通过提供具有第一导电类型的掺杂的半导体衬底来制造保护结构。 在半导体衬底的表面上施加具有第二导电类型掺杂的半导体层。 在半导体层的第一区域中形成具有第二导电类型的掺杂的掩埋层，在半导体层和半导体衬底之间的接合处产生一层。 在掩埋层上方的半导体层的第一区域中形成具有第一导电类型掺杂的第一掺杂区。 在半导体层的第二区域中形成具有第二导电类型掺杂的第二掺杂区。 在半导体层的第一和第二区域之间形成电绝缘。 形成用于第一和第二掺杂剂区域的公共连接装置。