公开(公告)号：US07211769B2

公开(公告)日：2007-05-01

申请号：US10115111

申请日：2002-04-01

申请人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Ju-Young Yun ,  Gil-Heyun Choi

发明人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Ju-Young Yun ,  Gil-Heyun Choi

IPC分类号： F27B5/14

CPC分类号： H01L21/67109 ,  C30B25/10 ,  C30B31/14

摘要： A heating chamber which can be used during a reflow process to form a metal wiring having a multi-layered writing structure and a method of heating a wafer using the same, are provided. The heating chamber is movable upward and downward between the upper process position and the lower loading position, and includes a pedestal having a supporting surface for supporting a wafer, a cover installed above the pedestal to form a processing area together with the supporting surface when the pedestal is placed in its raised process position and a heating unit for heating the waver. In the method of heating the wafer, the temperature in the processing area is maintained suitable for heating the wafer before the wafer is loaded onto the supporting surface, the wafer is loaded onto the supporting surface and the loaded wafer is heating in the processing area.

摘要翻译： 提供了可以在回流工艺期间使用以形成具有多层书写结构的金属布线的加热室和使用其加热晶片的方法。 加热室可以在上部处理位置和下部装载位置之间上下移动，并且包括具有用于支撑晶片的支撑表面的基座，安装在基座上方的盖子，当与该支撑表面一起形成处理区域时 基座放置在其升高的处理位置和用于加热摇摆的加热单元。 在加热晶片的方法中，在将晶片加载到支撑表面之前，处理区域中的温度保持适于加热晶片，晶片被加载到支撑表面上，并且加载的晶片在处理区域中被加热。

公开(公告)号：US06787468B2

公开(公告)日：2004-09-07

申请号：US10035257

申请日：2002-01-04

申请人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

发明人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

IPC分类号： H01L2144

CPC分类号： H01L21/76844 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76882 ,  H01L2221/1089

摘要： A method of fabricating a semiconductor device having a recess region in an insulation layer on a silicon substrate, comprising the steps of depositing a barrier metal over the entire surface of the insulation layer including the substrate surface in the recess region, depositing selectively an anti-nucleation layer on the barrier metal except in the recess region, depositing a CVD-Al layer on the barrier metal in the recess region, depositing a metal or a metal alloy inhibiting aluminum migration on the anti-nucleation layer and the barrier metal except in the recess region, and depositing a PVD-Al layer and re-flowing the PVD-Al layer, for improving the quality of aluminum grooves. The present method inhibits PVD-Al migration and grain growth, which results in preventing abnormal patterning in the semiconductor device.

摘要翻译： 一种制造在硅衬底上的绝缘层中具有凹陷区域的半导体器件的方法，包括以下步骤：在包括凹陷区域中的衬底表面的绝缘层的整个表面上沉积阻挡金属， 在凹陷区域之外的阻挡金属上的成核层，在凹陷区域中的阻挡金属上沉积CVD-Al层，在抗成核层和除了在...中形成的阻挡金属之外沉积抑制铝迁移的金属或金属合金 并且沉积PVD-Al层并再次流动PVD-Al层，以改善铝槽的质量。 本方法抑制PVD-Al迁移和晶粒生长，这导致防止半导体器件中的异常图案化。

公开(公告)号：US06699790B2

公开(公告)日：2004-03-02

申请号：US10035807

申请日：2002-01-04

申请人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

发明人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

IPC分类号： H01L21443

CPC分类号： H01L21/76876 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76882

摘要： A semiconductor device fabrication method having a recess region in an insulation layer on a silicon substrate, includes the steps of depositing a barrier metal on an entire surface of the insulation layer, filling the recess region with an oxide layer, removing the barrier metal on an upper side of the insulation layer, removing the oxide layer in the recess region and exposing the barrier metal of the recess region, depositing a CVD-Al layer on the barrier metal, and depositing a PVD-Al layer on the CVD-Al layer and re-flowing the PVD-Al layer. The fabrication method of a semiconductor integrated circuit according to the present invention selectively removes a barrier metal in the outside of the recess region to expose the insulation layer to the air, and deposits the CVD-Al layer and the PVD-Al layer, which results in controlling abnormal growth of the CVD-Al metal.

摘要翻译： 一种在硅衬底上的绝缘层中具有凹陷区域的半导体器件制造方法，包括以下步骤：在绝缘层的整个表面上沉积阻挡金属，用氧化物层填充该凹陷区域， 去除所述凹陷区域中的氧化物层并暴露所述凹陷区域的阻挡金属，在所述阻挡金属上沉积CVD-Al层，以及在所述CVD-Al层上沉积PVD-Al层，以及 重新流动PVD-Al层。 根据本发明的半导体集成电路的制造方法选择性地去除凹陷区域的外部的阻挡金属以将绝缘层暴露于空气，并沉积CVD-Al层和PVD-Al层，这导致 控制CVD-Al金属的异常生长。

公开(公告)号：US20140070300A1

公开(公告)日：2014-03-13

申请号：US13724187

申请日：2012-12-21

申请人： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

发明人： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

摘要翻译： 半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体 层在垂直方向。 这些部分中的至少一些是相邻的多个通道的相应通道。 每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极 或填充层图案。

公开(公告)号：US20110303970A1

公开(公告)日：2011-12-15

申请号：US13104377

申请日：2011-05-10

申请人： Jin-Gyun Kim ,  Myoung-Bum Lee

发明人： Jin-Gyun Kim ,  Myoung-Bum Lee

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A vertical semiconductor device and a method of making a vertical semiconductor device include a first semiconductor pattern formed on a substrate and a first gate structure formed on a sidewall of the first semiconductor pattern. A second semiconductor pattern is formed on the first semiconductor pattern. A plurality of insulating interlayer patterns is formed on sidewalls of the second semiconductor pattern. The insulating interlayer patterns are spaced apart from each other to define grooves between the insulating interlayer patterns. The plurality of second gate structures is disposed in the grooves, respectively.

摘要翻译： 垂直半导体器件和制造垂直半导体器件的方法包括形成在衬底上的第一半导体图案和形成在第一半导体图案的侧壁上的第一栅极结构。 在第一半导体图案上形成第二半导体图案。 在第二半导体图案的侧壁上形成多个绝缘层间图案。 绝缘层间图案彼此间隔开以限定绝缘层间图案之间的凹槽。 多个第二栅极结构分别设置在槽中。

公开(公告)号：US20110237055A1

公开(公告)日：2011-09-29

申请号：US13053291

申请日：2011-03-22

申请人： Yong-hoon Son ,  Si-Young Choi ,  Myoung-Bum Lee ,  Ki-Hyun Hwang ,  Seung-Jae Baik ,  Jeong Hee Han

发明人： Yong-hoon Son ,  Si-Young Choi ,  Myoung-Bum Lee ,  Ki-Hyun Hwang ,  Seung-Jae Baik ,  Jeong Hee Han

IPC分类号： H01L21/20

CPC分类号： H01L27/11578 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1207

摘要： A stacked semiconductor device that is reliable by forming an insulating layer on a lower memory layer and by forming a single crystalline semiconductor in portions of the insulating layer. A method of manufacturing the stacked semiconductor device, including: providing a lower memory layer including a plurality of lower memory structures; forming an insulating layer on the lower memory layer; forming trenches by removing portions of the insulating layer; forming a preparatory semiconductor layer for filling the trenches; and forming a single crystalline semiconductor layer by phase-changing the preparatory semiconductor layer.

摘要翻译： 通过在下部存储层上形成绝缘层，在绝缘层的一部分形成单晶半导体，可靠的叠层型半导体装置。 一种制造叠层半导体器件的方法，包括：提供包括多个下部存储结构的下部存储层; 在下部存储层上形成绝缘层; 通过去除绝缘层的部分形成沟槽; 形成用于填充沟槽的准备半导体层; 以及通过相变所述预备半导体层来形成单晶半导体层。

公开(公告)号：US08916922B2

公开(公告)日：2014-12-23

申请号：US13724187

申请日：2012-12-21

申请人： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

发明人： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

摘要翻译： 半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体 层在垂直方向。 这些部分中的至少一些是相邻的多个通道的相应通道。 每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极 或填充层图案。

公开(公告)号：US06858529B2

公开(公告)日：2005-02-22

申请号：US10440777

申请日：2003-05-19

申请人： Eun-Ae Chung ,  Myoung-Bum Lee ,  Young-Pil Kim ,  Jin-Gyun Kim ,  Bean-Jun Jin

发明人： Eun-Ae Chung ,  Myoung-Bum Lee ,  Young-Pil Kim ,  Jin-Gyun Kim ,  Bean-Jun Jin

IPC分类号： H01L21/28 ,  H01L21/225 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/2257 ,  H01L21/28525 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.

摘要翻译： 形成半导体器件可以包括在包括其导电区域的半导体衬底上形成绝缘层，其中绝缘层具有暴露导电区域的一部分的接触孔。 可以在接触孔中形成多晶硅接触插塞，其中多晶硅接触插塞的至少一部分掺杂有具有小于磷（P）的扩散系数的扩散系数的元件。 还讨论了相关结构。

公开(公告)号：US5560778A

公开(公告)日：1996-10-01

申请号：US465015

申请日：1995-06-05

申请人： In-Seon Park ,  Myoung-Bum Lee ,  Chang-Gee Hong ,  Chang-Gyu Kim ,  U-In Chung

发明人： In-Seon Park ,  Myoung-Bum Lee ,  Chang-Gee Hong ,  Chang-Gyu Kim ,  U-In Chung

IPC分类号： H01L21/205 ,  C23C16/02 ,  C23C16/40 ,  C23C16/44 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  C23C16/00

CPC分类号： H01L21/02164 ,  C23C16/0245 ,  C23C16/402 ,  C23C16/44 ,  H01L21/02271 ,  H01L21/02315 ,  H01L21/31051 ,  H01L21/31608

摘要： A deposition rate of a dielectric material is varied with the electrical polarity of an underlying layer to obtain excellent deposition and planarization characteristics. A conductive layer and the underlying dielectric are surface-treated to have different electrical polarities so that the dielectric is formed by using the difference of deposition rates of the dielectric material between that on the conductive layer and that on the underlying dielectric. A CVD apparatus having a DC power source connected between a susceptor and a gas injection portion thereof is provided. The deposition and planarization can be performed at low temperatures and are simplified in process.

摘要翻译： 介电材料的沉积速率随着下层的电极性而变化，以获得优异的沉积和平坦化特性。 导电层和下面的电介质被表面处理以具有不同的电极性，使得通过使用电介质材料在导电层上和在下面的电介质之间的沉积速率的差异来形成电介质。 提供了一种具有连接在基座和其气体注入部分之间的直流电源的CVD装置。 沉积和平坦化可以在低温下进行并且在工艺上被简化。

公开(公告)号：US09040378B2

公开(公告)日：2015-05-26

申请号：US14309018

申请日：2014-06-19

申请人： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

发明人： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L21/28 ,  H01L21/02

CPC分类号： H01L27/11556 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

摘要： Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.

摘要翻译： 提供了使用这种方法形成的包括垂直沟道和半导体器件的半导体器件的形成方法。 所述方法可以包括形成堆叠，其包括与衬底的上表面上的多个导电图案交替的多个绝缘图案，并且通过堆叠形成孔。 孔可以暴露多个绝缘图案和多个导电图案的侧壁。 多个绝缘图案的侧壁可以沿着相对于衬底的上表面倾斜的第一平面对齐，并且多个导电图案的相应侧壁的中点可以沿着基本上 垂直于衬底的上表面。