公开(公告)号：US20160343565A1

公开(公告)日：2016-11-24

申请号：US15161892

申请日：2016-05-23

Applicant: CANON ANELVA CORPORATION

Inventor： Takuya SEINO ,  Manabu IKEMOTO ,  Kimiko MASHIMO

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/28

CPC classification number: H01L21/02049 ,  H01J37/32091 ,  H01J37/3244 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/67196 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66651

Abstract: It was found out that when radicals generated by plasma are fed to a treatment chamber via a plurality of holes (111) formed on a partition plate which separates a plasma-forming chamber (108) from the treatment chamber, and the radicals are mixed with a treatment gas which is separately fed to the treatment chamber, the excitation energy of the radicals is suppressed and thereby the substrate surface treatment at high Si-selectivity becomes possible, which makes it possible to conduct the surface treatment of removing native oxide film and organic matter without deteriorating the flatness of the substrate surface. The radicals in the plasma are fed to the treatment chamber via radical-passing holes (111) of a plasma-confinement electrode plate (110) for plasma separation, the treatment gas is fed to the treatment chamber (121) to be mixed with the radicals in the treatment chamber, and then the substrate surface is cleaned by the mixed atmosphere of the radicals and the treatment gas.

Abstract translation: 已经发现，当通过等离子体形成室（108）与处理室分离的分隔板上形成的多个孔（111）将由等离子体产生的自由基供给到处理室时，将自由基与 单独供给到处理室的处理气体被抑制，自由基的激发能被抑制，从而可以在高Si选择性下进行基板表面处理，这使得可以进行去除自然氧化膜和有机物的表面处理 而不会降低基板表面的平坦度。 通过用于等离子体分离的等离子体约束电极板（110）的自由基通过孔（111）将等离子体中的自由基供给到处理室，将处理气体供给到处理室（121）以与 处理室中的自由基，然后通过自由基和处理气体的混合气氛清洁基板表面。

公开(公告)号：US20140319676A1

公开(公告)日：2014-10-30

申请号：US14327985

申请日：2014-07-10

Applicant: CANON ANELVA CORPORATION

Inventor： Akira MATSUO ,  Yohsuke SHIBUYA ,  Naomu KITANO ,  Eitaroh MORIMOTO ,  Koji YAMAZAKI ,  Yu SATO ,  Takuya SEINO

IPC: H01L29/49 ,  H01L21/28

CPC classification number: H01L29/4966 ,  C23C14/046 ,  C23C14/345 ,  C23C14/35 ,  C23C14/5826 ,  C23C14/586 ,  H01J37/3402 ,  H01J37/3447 ,  H01J37/3452 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/823842 ,  H01L29/66545

Abstract: It is an object of the present invention to provide an electronic component manufacturing method, capable of suppressing reduction in a trench opening and suppressing diffusion of a metal film embedded in a trench. An embodiment of the present invention is an electronic component manufacturing method, including the steps of: forming a first electrode constituting layer (e.g., a TiAl film) in a recess (e.g., a trench) formed in a workpiece; forming an ultrathin barrier layer (e.g., a TiAlN film) by forming a nitride layer by plasma-nitriding a surface of the first electrode constituting layer; and forming a second electrode constituting layer (e.g., an Al wiring layer) on the ultrathin barrier layer.

Abstract translation: 本发明的目的是提供一种电子部件制造方法，能够抑制沟槽开口的减少和抑制嵌入在沟槽中的金属膜的扩散。 本发明的一个实施例是一种电子部件制造方法，包括以下步骤：在形成在工件中的凹部（例如沟槽）中形成第一电极构成层（例如TiAl膜）; 通过等离子体氮化第一电极构成层的表面形成氮化物层来形成超薄势垒层（例如，TiAlN膜）; 以及在所述超薄阻挡层上形成第二电极构成层（例如Al布线层）。

公开(公告)号：US20130071975A1

公开(公告)日：2013-03-21

申请号：US13675147

申请日：2012-11-13

Applicant: Canon Anelva Corporation

Inventor： Naomu KITANO ,  Takuya SEINO ,  Akira MATSUO ,  Yu SATO ,  Eitaro MORIMOTO

IPC: H01L21/285 ,  H01L29/66

CPC classification number: H01L21/28556 ,  C23C14/04 ,  C23C14/0641 ,  C23C14/351 ,  C23C14/54 ,  H01J37/34 ,  H01J37/345 ,  H01J37/3452 ,  H01J37/3455 ,  H01L21/2855 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a method and apparatus for manufacturing a semiconductor device using a PVD method and enabling achievement of a desired effective work function and reduction in leak current without increasing an equivalent oxide thickness. A method for manufacturing a semiconductor device in an embodiment of the present invention includes the steps of: preparing a substrate on which an insulating film having a relative permittivity higher than that of a silicon oxide film is formed; and depositing a metal nitride film on the insulating film. The metal nitride depositing step is a step of sputtering deposition in an evacuatable chamber using a metal target and a cusp magnetic field formed over a surface of the metal target by a magnet mechanism in which magnet pieces are arranged as grid points in such a grid form that the adjacent magnet pieces have their polarities reversed from each other.

Abstract translation: 本发明提供一种使用PVD方法制造半导体器件的方法和装置，并且能够实现期望的有效功函数并且在不增加等效氧化物厚度的情况下降低漏电流。 本发明的实施方式的半导体装置的制造方法包括以下步骤：制作其上形成有相对介电常数高于氧化硅膜的绝缘膜的基板; 以及在所述绝缘膜上沉积金属氮化物膜。 金属氮化物沉积步骤是使用金属靶溅射沉积在可抽出腔室中的步骤，并且通过磁体机构在金属靶材的表面上形成的尖点磁场，其中磁体块以这种格子形式布置为网格点 相邻的磁铁片的极性彼此相反。

公开(公告)号：US20140353149A1

公开(公告)日：2014-12-04

申请号：US14462860

申请日：2014-08-19

Applicant: CANON ANELVA CORPORATION

Inventor： Takuya SEINO ,  Kazumasa NISHIMURA ,  Koji TSUNEKAWA ,  Eisaku WATANABE ,  Shigeo KANEKO

IPC: H01L21/67

CPC classification number: H01L21/67184 ,  H01L21/67173 ,  H01L43/12

Abstract: The present invention provides a TMR element manufacturing apparatus capable of reducing contamination of impurities in magnetic films. According to an embodiment of the present invention, a tunnel magneto-resistance element manufacturing apparatus includes: a load lock device to load and unload a substrate from and to an outside; a first substrate transfer device that is connected to the load lock device, at least one substrate process device being connected to the first substrate transfer device; a first evacuation unit provided in the first substrate transfer device; a second substrate transfer device that is connected to the first substrate transfer device, multiple substrate process devices being connected to the second substrate transfer device; and a second evacuation unit provided in the second substrate transfer device. At least one of the multiple substrate process devices connected to the second substrate transfer device is an oxidation device.

Abstract translation: 本发明提供能够减少磁性膜中的杂质污染的TMR元件制造装置。 根据本发明的实施例，隧道磁阻元件制造装置包括：负载锁定装置，用于从外部加载和卸载基板; 连接到所述负载锁定装置的第一衬底传送装置，连接到所述第一衬底传送装置的至少一个衬底处理装置; 设置在所述第一基板输送装置中的第一排气单元; 连接到第一衬底传送装置的第二衬底传送装置，连接到第二衬底传送装置的多个衬底处理装置; 以及设置在第二基板输送装置中的第二排出单元。 连接到第二衬底转移装置的多个衬底工艺装置中的至少一个是氧化装置。