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    Apparatus and method for improving resolution of a current mode driver
    1.
    发明授权
    Apparatus and method for improving resolution of a current mode driver 有权
    用于提高电流模式驱动器的分辨率的装置和方法

    公开(公告)号：US07161513B2

    公开(公告)日：2007-01-09

    申请号：US09742250

    申请日：2000-12-20

    申请人： Carl Werner ,  Pak Shing Chau

    发明人： Carl Werner ,  Pak Shing Chau

    IPC分类号： H03M1/06

    CPC分类号： G11C7/1051 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0298 ,  H04L25/08 ,  H04L25/4902

    摘要： A method for improving resolution of a current mode driver. The current mode driver is operable to provide an output that falls within a predetermined range. An embodiment of the method includes sensing a condition, such as a process condition, a voltage condition and a temperature condition. A full scale current of a digital-to-analog converter is adjusted in accordance with the condition. A current control signal is set based on an output of the digital-to-analog converter. The sensing step may include measuring a process, voltage or temperature sensitive DC parameter. Alternatively, the sensing step may include sensing a process, voltage or temperature sensitive AC parameter.

    摘要翻译： 一种用于提高电流模式驱动器的分辨率的方法。 当前模式驱动器可操作以提供落在预定范围内的输出。 该方法的实施例包括感测诸如处理条件，电压条件和温度条件的条件。 根据条件调整数模转换器的满量程电流。 基于数模转换器的输出设置电流控制信号。 感测步骤可以包括测量过程，电压或温度敏感的DC参数。 或者，感测步骤可以包括感测过程，电压或温度敏感的AC参数。

    Method and apparatus for a mesochronous transmission system
    2.
    发明授权
    Method and apparatus for a mesochronous transmission system 有权
    中间传输系统的方法和装置

    公开(公告)号：US07978802B1

    公开(公告)日：2011-07-12

    申请号：US11974362

    申请日：2007-10-12

    申请人： Prasun K. Raha ,  Donald Stark ,  Dean Liu ,  Pak Shing Chau

    发明人： Prasun K. Raha ,  Donald Stark ,  Dean Liu ,  Pak Shing Chau

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0025 ,  H03L7/07 ,  H03L7/081 ,  H03L7/0814 ,  H03L7/087 ,  H04L7/0331

    摘要： A method and apparatus for a multiple lane transmission system that provides both a low latency mode of operation, while at the same time, provides reduced lane-lane skew. The overall transmission system operates as a mesochronous system, whereby each clock domain of the transmission system is synchronized to the leaf nodes of a global clock tree. A phase aligner is then used to align the phase of both the bit and byte clocks of each transmission lane to the clock signal generated at the leaf nodes of the global clock tree.

    摘要翻译： 一种用于多通道传输系统的方法和装置，其提供低等待时间操作模式，同时提供减少的车道歪斜。 整个传输系统作为中间同步系统工作，由此传输系统的每个时钟域与全局时钟树的叶节点同步。 然后使用相位对准器将每个传输通道的位和字节时钟的相位与在全局时钟树的叶节点处生成的时钟信号进行对准。

    Delay locked loop circuitry for clock delay adjustment
    4.
    发明授权
    Delay locked loop circuitry for clock delay adjustment 有权
    延迟锁定环电路，用于时钟延迟调整

    公开(公告)号：US06539072B1

    公开(公告)日：2003-03-25

    申请号：US09524402

    申请日：2000-03-13

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    IPC分类号： H04L700

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

    摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.

    摘要翻译： 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

    Delay-locked loop circuitry for clock delay adjustment
    5.
    发明授权
    Delay-locked loop circuitry for clock delay adjustment 失效
    用于时钟延迟调整的延迟锁定环路

    公开(公告)号：US6125157A

    公开(公告)日：2000-09-26

    申请号：US795657

    申请日：1997-02-06

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark

    IPC分类号： G06F1/10 ,  G11C7/22 ,  H03K5/00 ,  H03K5/13 ,  H03K5/24 ,  H03L7/07 ,  H03L7/081 ,  H04L7/00

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0037 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H04L7/0008 ,  H04L7/0025

    摘要： Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used.

    摘要翻译： 延迟锁定环路电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的一组延迟产生元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

    Circuitry for the delay adjustment of a clock signal
    6.
    发明授权
    Circuitry for the delay adjustment of a clock signal 失效
    电路用于时钟信号的延迟调整

    公开(公告)号：US5945862A

    公开(公告)日：1999-08-31

    申请号：US904203

    申请日：1997-07-31

    申请人： Kevin S. Donnelly ,  Jun Kim ,  Bruno W. Garlepp ,  Mark A. Horowitz ,  Thomas H. Lee ,  Pak Shing Chau ,  Jared L. Zerbe ,  Clemenz L. Portmann ,  Yiu-Fai Chan

    发明人： Kevin S. Donnelly ,  Jun Kim ,  Bruno W. Garlepp ,  Mark A. Horowitz ,  Thomas H. Lee ,  Pak Shing Chau ,  Jared L. Zerbe ,  Clemenz L. Portmann ,  Yiu-Fai Chan

    IPC分类号： H03K5/13 ,  H03H11/26

    CPC分类号： H03K5/1565 ,  H03K5/13

    摘要： Circuitry for adjusting the phase of an incoming periodic signal, typically a clock signal, throughout the entire period of the periodic signal. Phase adjustment circuitry has high resolution and employs only the number of delay elements in a delay chain necessary to span at least the period of the incoming signal or at least half the period in the case of dual chains receiving complementary clocks. Phase adjustment circuitry includes a delay chain of having a plurality of taps, a boundary detector for indicating when a tap is at a phase boundary of the incoming periodic signal, and selection circuitry for selecting one of the taps from the delay chain based on the boundary detector output and the selection circuitry input such that the selected tap is the desired phase adjustment of the incoming periodic signal and that the delay of the incoming signal is adjustable across its phase boundaries. Phase interpolation between the taps of the delay chain is employed to increase the resolution of the adjustment to the periodic signal. Duty cycle correction of the input clock and the selected output clock is employed to improve accuracy.

    摘要翻译： 用于在整个周期信号的整个周期内调整进入周期信号（通常为时钟信号）的相位的电路。 相位调整电路具有高分辨率，并且仅在延迟链中仅使用延伸元件的数量来跨越至少输入信号的周期，或者在双链接收互补时钟的情况下至少半个周期。 相位调整电路包括具有多个抽头的延迟链，边界检测器，用于指示抽头何时处于输入周期性信号的相位边界;以及选择电路，用于基于边界从延迟链中选择一个抽头 检测器输出和选择电路输入，使得所选择的抽头是输入周期性信号的期望的相位调整，并且输入信号的延迟在其相位边界上是可调节的。 使用延迟链的抽头之间的相位插值来增加对周期性信号的调整的分辨率。 采用输入时钟和选择的输出时钟的占空比校正来提高精度。

    Method and apparatus for evaluating and optimizing a signaling system
    10.
    发明授权
    Method and apparatus for evaluating and optimizing a signaling system 有权
    用于评估和优化信号系统的方法和装置

    公开(公告)号：US07137048B2

    公开(公告)日：2006-11-14

    申请号：US09976170

    申请日：2001-10-12

    申请人： Jared Zerbe ,  Pak Shing Chau ,  William Franklin Stonecypher

    发明人： Jared Zerbe ,  Pak Shing Chau ,  William Franklin Stonecypher

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31717 ,  G01R31/31703 ,  G01R31/3183 ,  G06F11/221 ,  H04B3/32

    摘要： A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the invention may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the invention may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

    摘要翻译： 描述了用于评估和优化信令系统的方法和装置。 在系统的发送电路中产生测试信息的模式，并将其发送到接收电路。 在接收电路中产生类似的信息模式并用作参考。 接收电路比较图案。 模式之间的任何差异是可观察的。 在一个实施例中，实现线性反馈移位寄存器（LFSR）以产生模式。 本发明的一个实施例可以用各种类型的信令系统来实现，包括具有单端信号和具有差分信号的信号系统。 本发明的实施例可以应用于在给定时间在单个导体上传送单个信息位的系统和同时在单个导体上传送多个信息位的系统。