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    Ferroelectric flat panel displays
    2.
    发明授权
    Ferroelectric flat panel displays 失效
    铁电平板显示屏

    公开(公告)号：US06198225B1

    公开(公告)日：2001-03-06

    申请号：US09326838

    申请日：1999-06-07

    申请人： Gota Kano ,  Yasuhiro Shimada ,  Shinichiro Hayashi ,  Koji Arita ,  Carlos A. Paz de Araujo ,  Joseph D. Cuchiaro ,  Larry D. McMillan

    发明人： Gota Kano ,  Yasuhiro Shimada ,  Shinichiro Hayashi ,  Koji Arita ,  Carlos A. Paz de Araujo ,  Joseph D. Cuchiaro ,  Larry D. McMillan

    IPC分类号： G09G310

    CPC分类号： G09G3/367 ,  G09G3/22 ,  H01J1/30 ,  H01J2201/306 ,  H01J2329/00

    摘要： A thin film of ferroelectric layered superlattice material in a flat panel display device is energized to selectively influence the display image. In one embodiment, a voltage pulse causes the layered superlattice material to emit electrons that impinge upon a phosphor, causing the phosphor to emit light. In another embodiment, an electric potential creates a remanent polarization in the layered superlattice material, which exerts an electric field in liquid crystal layer, thereby influencing the transmissivity of light through the liquid crystal. The layered superlattice material is a metal oxide formed using an inventive liquid precursor containing an alkoxycarboxylate. The thin film thickness is preferably in the range 50-140 nm, so that polarizabilty and transparency of the thin film is enhanced. A display element may comprise a varistor device to prevent cross-talk between pixels and to enable sudden polarization switching. A functional gradient in the ferroelectric thin film enhances electron emission. Two ferroelectric elements, one on either side of the phosphor may be used to enhance luminescence. A phosphor can be sandwiched between a dielectric and a ferroelectric to enhance emission.

    摘要翻译： 平板显示装置中的铁电层状超晶格材料薄膜被通电以选择性地影响显示图像。 在一个实施例中，电压脉冲使得层状超晶格材料发射撞击磷光体的电子，导致磷光体发光。 在另一个实施例中，电位在层状超晶格材料中产生剩余极化，其在液晶层中施加电场，从而影响透过液晶的透射率。 层状超晶格材料是使用本发明的含有烷氧基羧酸盐的液体前体形成的金属氧化物。 薄膜厚度优选在50-140nm的范围内，从而提高薄膜的极化性和透明度。 显示元件可以包括用于防止像素之间的串扰并允许突发极化切换的变阻器装置。 铁电薄膜中的功能梯度增强了电子发射。 可以使用两个铁电元件，一个在荧光体的两侧，以增强发光。 荧光体可以夹在电介质和铁电体之间以增强发射。

    Negative-resistance semiconductor device
    4.
    发明授权
    Negative-resistance semiconductor device 失效
    负电阻半导体器件

    公开(公告)号：US4117587A

    公开(公告)日：1978-10-03

    申请号：US712583

    申请日：1976-08-06

    申请人： Gota Kano ,  Hitoo Iwasa

    发明人： Gota Kano ,  Hitoo Iwasa

    IPC分类号： G11C11/36 ,  G11C11/412 ,  H01L21/82 ,  H01L27/098 ,  H03K3/3565 ,  B01J17/00

    CPC分类号： H03K3/3565 ,  G11C11/36 ,  G11C11/412 ,  H01L21/82 ,  H01L27/098 ,  G11C2211/5614

    摘要： A pair of field-effect transistors (hereinafter referred to as FETs) of p-channel type and n-channel type, respectively, both to be electrically actuated in a depletion mode, are formed on a single semiconductor substrate, for instance, a single silicon substrate, and both sources or both drains are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, whereby the pair of FETs are series-connected, and the gate electrode of each FET is connected to the drain electrode or the source electrode that is not series connected in the above-mentioned way, respectively, of the other FET. The device is characterized in that each FET has each back-gate electrode region behind the channel. Preferably, such back-gate regions are high-doped diffused regions.When a voltage of specified range is applied across both non-series-connected electrodes, i.e., the two external terminals, the resulting voltage-current characteristic presents a so-called dynatron-type characteristic, producing a negative-resistance phenomenon over a fairly wide range of applied voltage. Since this device is, as seen from outside as one device, a two-terminal device constituted on a single substrate comprising FETs with back-gate electrode, it is not only fit to be highly integrated but also able to produce a state of virtually zero value of cut-off current. Consequently, this device can be utilized for switching, memorization, large amplitude oscillation, and other various uses, with low Vth2 value.

    摘要翻译： 在单个半导体衬底上形成分别以耗尽模式电致动的p沟道型和n沟道型的一对场效应晶体管（以下称为FET），例如单个 硅衬底，两个源极或两个漏极彼此连接，或者一个FET的源极和另一个FET的漏极彼此连接，由此一对FET串联连接，并且每个FET的栅极电极 FET分别与另一个FET分别以上述方式串联的漏电极或源极连接。 该器件的特征在于每个FET在通道后面具有每个背栅极电极区域。 优选地，这种背栅极区域是高掺杂扩散区域。

    Selective thermal oxidation of As-containing compound semiconductor regions
    5.
    发明授权
    Selective thermal oxidation of As-containing compound semiconductor regions 失效
    含砷化合物半导体区域的选择性热氧化

    公开(公告)号：US4194927A

    公开(公告)日：1980-03-25

    申请号：US923689

    申请日：1978-07-11

    申请人： Hiromitsu Takagi ,  Gota Kano ,  Iwao Teramoto

    发明人： Hiromitsu Takagi ,  Gota Kano ,  Iwao Teramoto

    IPC分类号： H01L21/3105 ,  H01L21/324 ,  H01L7/36 ,  H01L7/44

    CPC分类号： H01L21/3105 ,  H01L21/3245

    摘要： In the process of forming a thermal oxide film or heat treatment of an oxide film in making a semiconductor device comprising a compound semiconductor of arsenic, the semiconductor is handled in an atmosphere containing arsenic oxide vapor in order to prevent evaporation of the arsenic tri-oxide in the thermal oxidation film or the oxide film under heat treatment, thereby to form a thermal oxide film having good chemical stability and good electrical characteristics, or to improve the oxide film so as to have good chemical stability and good electrical characteristics.

    摘要翻译： 在制造包含砷化合物半导体的半导体器件中形成热氧化膜或氧化膜的热处理的过程中，在含有氧化砷蒸汽的气氛中处理半导体，以防止三氧化砷的蒸发 在热氧化膜或氧化膜中进行热处理，从而形成具有良好的化学稳定性和良好的电特性的热氧化膜，或改善氧化膜以具有良好的化学稳定性和良好的电特性。

    Apparatus to prevent overcurrent or overvoltage
    6.
    发明授权
    Apparatus to prevent overcurrent or overvoltage 失效
    防止过电流或过电压的装置

    公开(公告)号：US3992650A

    公开(公告)日：1976-11-16

    申请号：US545165

    申请日：1975-01-29

    申请人： Hitoo Iwasa ,  Gota Kano

    发明人： Hitoo Iwasa ,  Gota Kano

    IPC分类号： H02H3/087 ,  H02H3/20 ,  H02H3/08

    CPC分类号： H02H3/087

    摘要： Across a D.C. power source 1, a load 2, a switching element 4, such as a transistor having a control electrode c (base), and a voltage detection means 5, such as a resistor, are connected in series, and a known negative resistance device 6, having two terminals 31 and 32, is connected by its one terminal 32 to said control electrode c of the switching element 4 and by its other terminal 31 to one end of said series resistor 5 which one end is opposite to that connected to said switching element (4), wherein said negative resistance device 6 comprises, as shown in FIG 2, known complementary connection of a depletion mode n-channel field-effect transistor (FET) and a depletion mode p-channel FET. The FETs are connected from source to source, and from the gate of each to the drain of the other so that when an overcurrent to the load 2 or an overvoltage at the voltage source 1 occurs, voltage across said resistor 5 exceeds a preset value, the negative resistance device 6 is cut-off, thereby cutting off the switching element 4.

    摘要翻译： 跨直流电源1，负载2，具有控制电极c（基极）的晶体管等开关元件4以及诸如电阻器的电压检测装置5串联连接，已知的负极 具有两个端子31和32的电阻装置6通过其一个端子32连接到开关元件4的所述控制电极c，并且其另一个端子31连接到所述串联电阻器5的一端，其一端与连接 到所述开关元件（4），其中如图2所示，所述负电阻器件6包括耗尽型n沟道场效应晶体管（FET）和耗尽型p沟道FET的已知互补连接。 FET从源极到源极，从每个的栅极连接到另一个的漏极，使得当发生到负载2的过电流或电压源1的过电压时，所述电阻器5两端的电压超过预设值， 负电阻装置6被切断，从而切断开关元件4。

    Field effect transistor
    7.
    发明授权
    Field effect transistor 失效
    场效应晶体管

    公开(公告)号：US4459556A

    公开(公告)日：1984-07-10

    申请号：US539634

    申请日：1983-10-07

    申请人： Shutaro Nanbu ,  Atsushi Nagashima ,  Gota Kano

    发明人： Shutaro Nanbu ,  Atsushi Nagashima ,  Gota Kano

    IPC分类号： H01L29/80 ,  H01L29/812 ,  H01L29/76

    CPC分类号： H01L29/8124

    摘要： A dual gate Schottky barrier gate GaAs FET with improved cross-modulation characteristics when used in a UHF gain controlling tuner, having a value of 40 mA or smaller of a drain to source saturation current, the improvement of the FET is that length of a second gate which is disposed between a first gate and a drain is 1.5 .mu.m or longer.

    摘要翻译： 当在UHF增益控制调谐器中使用具有40mA或更小的漏极到源极饱和电流的值时，具有改进的交叉调制特性的双栅肖特基势垒栅极GaAs FET，FET的改进是第二 设置在第一栅极和漏极之间的栅极为1.5μm以上。

    Method of manufacturing a junction field effect transistor
    9.
    发明授权
    Method of manufacturing a junction field effect transistor 失效
    连接场效应晶体管的制造方法

    公开(公告)号：US3951702A

    公开(公告)日：1976-04-20

    申请号：US460877

    申请日：1974-04-15

    申请人： Gota Kano ,  Satoshi Teramoto

    发明人： Gota Kano ,  Satoshi Teramoto

    IPC分类号： H01L29/80 ,  H01L21/22 ,  H01L21/337 ,  H01L29/00 ,  H01L29/808 ,  H01L21/225

    CPC分类号： H01L29/00 ,  H01L29/66901

    摘要： A method of manufacturing a junction field effect transistor wherein after a P type pre-diffused layer is formed in an N type region constituting a back gate region of a junction field effect transistor, arsenic is selectively diffused into the P type pre-diffused layer to form a gate region with a simultaneous drive-in step for the P type pre-diffused layer in order to obtain a thin channel by utilizing the pull-in effect.

    摘要翻译： 一种结型场效应晶体管的制造方法，其中，在形成结型场效应晶体管的背栅区域的N型区域中形成P型预扩散层后，砷选择性地扩散到P​​型预扩散层 形成具有用于P型预扩散层的同时驱动步骤的栅极区域，以便通过利用拉入效应来获得薄沟道。

    Method of making FET utilizing shadow masking and diffusion from a doped oxide
    10.
    发明授权
    Method of making FET utilizing shadow masking and diffusion from a doped oxide 失效
    利用阴影掩蔽和掺杂氧化物扩散制造FET的方法

    公开(公告)号：US4351099A

    公开(公告)日：1982-09-28

    申请号：US149621

    申请日：1980-05-12

    申请人： Hiromitsu Takagi ,  Shotaro Umebachi ,  Gota Kano ,  Iwao Teramoto

    发明人： Hiromitsu Takagi ,  Shotaro Umebachi ,  Gota Kano ,  Iwao Teramoto

    IPC分类号： H01L21/033 ,  H01L21/337 ,  H01L29/80 ,  H01L29/808 ,  H01L21/31 ,  H01L21/225 ,  H01L21/265

    CPC分类号： H01L29/66909 ,  H01L21/033 ,  H01L29/80 ,  H01L29/808

    摘要： A novel self-align type method of making an FET with a very short gate length and a good high frequency characteristic, and a low noise characteristic, the method comprising the steps of:forming on a silicon epitaxial layer (13) of n-type conductivity a doped oxide film (14) containing boron as an impurity to give p-type conductivity,forming a mask (15a, 16a) containing Si.sub.3 N.sub.4 film and having a width larger than that of a gate region (19) to be formed on said n-type epitaxial layer (13),etching said doped oxide film (14) by utilizing said mask (15a, 16a) as an etching mask to expose surface of said silicon crystal layer (13) in a manner that sides of the part of said doped oxide film (14) covered by said mask (15, 16a) are side-etched by a predetermined width,ion-implanting an impurity of said first conductivity type into said n-type epitaxial layer (13) by utilizing said mask as implanting mask, andcarrying out a heat treating thereby diffusing said second conductivity type impurity from said doped oxide film (14) retained only under said mask into said n-type epitaxial layer (13) to form said gate region (19) and driving said ion-implanted first conductivity type impurity into said silicon crystal layer (13) to form a source region (17) and a drain region (18).

    摘要翻译： 一种制造具有非常短的栅极长度和良好的高频特性以及低噪声特性的FET的新型自对准型方法，该方法包括以下步骤：在n型硅外延层（13）上形成 电导率为含有硼作为杂质的掺杂氧化物膜（14）以产生p型导电性，形成包含Si 3 N 4膜的掩模（15a，16a），其宽度大于所述栅极区域（19）的宽度 通过利用所述掩模（15a，16a）作为蚀刻掩模蚀刻所述掺杂氧化物膜（14），以使得所述硅晶体层（13）的所述一部分的侧面 将由所述掩模（15,16a）覆盖的所述掺杂氧化物膜（14）以预定宽度进行侧蚀刻，通过利用所述掩模将所述第一导电类型的杂质离子注入所述n型外延层（13） 植入掩模，并进行热处理，从而扩散所述第二导电型不动杆 将所述掺杂氧化物膜（14）保留在所述掩模内的所述n型外延层（13）中以形成所述栅极区域（19）并将所述离子注入的第一导电类型杂质驱动到所述硅晶体层（13）中， 以形成源极区（17）和漏极区（18）。