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    PROCESS APPARATUSES
    1.
    发明申请
    PROCESS APPARATUSES 有权
    过程设备

    公开(公告)号：US20070267461A1

    公开(公告)日：2007-11-22

    申请号：US11419933

    申请日：2006-05-23

    申请人： Chen-Hua Yu ,  Minghsing Tsai ,  Yi-Li Hsiao

    发明人： Chen-Hua Yu ,  Minghsing Tsai ,  Yi-Li Hsiao

    IPC分类号： A47J36/02

    CPC分类号： H01L21/67196 ,  H01L21/67017 ,  H01L21/76849 ,  H01L21/76883

    摘要： An apparatus includes an enclosure, at least one process chamber, a robot and at least one valve. The enclosure has a gas therein and at least one door configured to cover an opening into the enclosure. The gas includes at least one reduction gas. The robot is disposed within the enclosure and configured to transfer a substrate between the door and the process chamber. The valve is coupled to the enclosure.

    摘要翻译： 一种装置包括外壳，至少一个处理室，机​​器人和至少一个阀。 外壳中具有气体，并且至少一个门构造成覆盖到外壳中的开口。 气体包括至少一种还原气体。 机器人设置在外壳内并且构造成在门和处理室之间传送基板。 阀连接到外壳。

    Passivation structure for semiconductor devices
    3.
    发明申请
    Passivation structure for semiconductor devices 审中-公开
    半导体器件钝化结构

    公开(公告)号：US20060138668A1

    公开(公告)日：2006-06-29

    申请号：US11023296

    申请日：2004-12-27

    申请人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Minghsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Minghsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L23/06

    CPC分类号： H01L23/53238 ,  H01L21/288 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76865 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for providing a passivation structure for semiconductor devices is provided. In an embodiment, the passivation structure comprises a first barrier layer and a second barrier layer, wherein the second barrier layer may comprise a material, such as cobalt and/or nickel, that is less pure than the first barrier layer. In another embodiment, a single gradient barrier layer is formed. In this embodiment the single gradient barrier layer exhibits a greater pure conductive material, such as cobalt and/or nickel, nearer the conductive line than near the surface.

    摘要翻译： 提供了一种用于提供半导体器件的钝化结构的系统和方法。 在一个实施例中，钝化结构包括第一阻挡层和第二阻挡层，其中第二阻挡层可以包括比第一阻挡层更纯的材料，例如钴和/或镍。 在另一个实施例中，形成单个梯度阻挡层。 在该实施例中，单个梯度阻挡层表现出比在表面附近更靠近导电线的较高纯度的导电材料，例如钴和/或镍。

    Process for Improving Copper Line Cap Formation
    4.
    发明申请
    Process for Improving Copper Line Cap Formation 有权
    改善铜线帽形成的工艺

    公开(公告)号：US20120190191A1

    公开(公告)日：2012-07-26

    申请号：US13440704

    申请日：2012-04-05

    申请人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

    发明人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76865 ,  H01L21/76883

    摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.

    摘要翻译： 集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层 开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。 集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在 导线。

    COOLING MECHANISM FOR STACKED DIE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    COOLING MECHANISM FOR STACKED DIE PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    堆叠式包装的冷却机构及其制造方法

    公开(公告)号：US20120061059A1

    公开(公告)日：2012-03-15

    申请号：US13033840

    申请日：2011-02-24

    申请人： Yi-Li HSIAO ,  Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung ,  Chun Hui Yu

    发明人： Yi-Li HSIAO ,  Chen-Hua Yu ,  Da-Yuan Shih ,  Chih-Hang Tung ,  Chun Hui Yu

    IPC分类号： F28D15/00

    CPC分类号： F28D15/02 ,  H01L23/34 ,  H01L23/473 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/0401

    摘要： An apparatus for cooling a stacked die package comprises a first die provided above a substrate; a second die above the first die; a cooling fluid in fluid communication with the first die and the second die, the cooling fluid for absorbing thermal energy from the first and the second die; a housing containing the first and second dies, the housing sealing the first and second dies from an environment, wherein the housing further includes a first opening and a second opening, the first and second openings being vertically displaced from one another; a conduit having one end connected to the first opening and the other end connected to the second opening, the conduit allowing the cooling liquid to circulate from the first opening to the second opening; a first temperature sensor being arranged to provide an output that is dependent on a local temperature at the first opening; and a second temperature sensor being arranged to provide an output that is dependent on a local temperature at the second opening, wherein the outputs of the first and second temperature sensors relative to each other are indicative of a level of the cooling fluid.

    摘要翻译： 一种用于冷却堆叠的管芯封装的设备，包括设置在衬底上的第一管芯; 第一个模具上方的第二个模具; 与第一模具和第二模具流体连通的冷却流体，用于从第一模具和第二模具吸收热能的冷却流体; 壳体，其包含第一和第二模具，所述壳体将环境中的第一和第二模具密封，其中所述壳体还包括第一开口和第二开口，所述第一和第二开口彼此垂直移位; 导管，其一端连接到第一开口，另一端连接到第二开口，导管允许冷却液从第一开口循环到第二开口; 第一温度传感器被布置成提供依赖于第一开口处的局部温度的输出; 并且第二温度传感器被布置成提供取决于第二开口处的局部温度的输出，其中第一和第二温度传感器相对于彼此的输出指示冷却流体的水平。

    Substrate carrier and facility interface and apparatus including same
    8.
    发明授权
    Substrate carrier and facility interface and apparatus including same 有权
    基板载体和设备接口及其设备

    公开(公告)号：US07418982B2

    公开(公告)日：2008-09-02

    申请号：US11419914

    申请日：2006-05-23

    申请人： Chen-Hua Yu ,  Yi-Li Hsiao

    发明人： Chen-Hua Yu ,  Yi-Li Hsiao

    IPC分类号： B65B1/04

    CPC分类号： H01L21/67376 ,  H01L21/67393 ,  H01L21/67772

    摘要： A carrier comprises an enclosure, a cabinet and at least one substrate holder. The enclosure comprises a door. The cabinet is coupled to the carrier. The cabinet comprises at least one valve and contains at least one reduction fluid. The substrate holder is disposed within the enclosure to support at least one substrate.

    摘要翻译： 载体包括外壳，机壳和至少一个基板保持器。 外壳包括一个门。 机柜耦合到载体。 所述柜包括至少一个阀并且包含至少一个还原流体。 衬底保持器设置在外壳内以支撑至少一个衬底。

    Process for improving copper line cap formation
    9.
    发明授权
    Process for improving copper line cap formation 有权
    改善铜线帽形成的工艺

    公开(公告)号：US08623760B2

    公开(公告)日：2014-01-07

    申请号：US13440704

    申请日：2012-04-05

    申请人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

    发明人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76865 ,  H01L21/76883

    摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.

    摘要翻译： 集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层 开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。 集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在 导线。

    Process for improving copper line cap formation
    10.
    发明授权
    Process for improving copper line cap formation 有权
    改善铜线帽形成的工艺

    公开(公告)号：US08193087B2

    公开(公告)日：2012-06-05

    申请号：US11605893

    申请日：2006-11-28

    申请人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

    发明人： Chien-Hsueh Shih ,  Minghsing Tsai ,  Chen-Hua Yu ,  Ming-Shih Yeh

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76865 ,  H01L21/76883

    摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.

    摘要翻译： 集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层 开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。 集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在 导线。