专利检索 ap:("Yi-Li Hsiao" OR "Chen-Hua Yu" OR "Shin-Puu Jeng" OR "Chih-Hang Tung" OR "Cheng-Chang Wei") AND inv:"Chen-Hua Yu" 第 1 页

1.

发明申请
Semiconductor Device and Bump Formation Process 审中-公开
标题翻译：半导体器件和凸块形成工艺

公开(公告)号：US20110186989A1

公开(公告)日：2011-08-04

申请号：US12883950

申请日：2010-09-16

申请人： Yi-Li Hsiao , Chen-Hua Yu , Shin-Puu Jeng , Chih-Hang Tung , Cheng-Chang Wei

发明人： Yi-Li Hsiao , Chen-Hua Yu , Shin-Puu Jeng , Chih-Hang Tung , Cheng-Chang Wei

IPC分类号： H01L23/52 , H01L21/44

CPC分类号： H01L24/11 , H01L21/44 , H01L21/76885 , H01L23/49811 , H01L23/52 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0347 , H01L2224/0361 , H01L2224/03912 , H01L2224/10126 , H01L2224/10145 , H01L2224/11 , H01L2224/1147 , H01L2224/11823 , H01L2224/11825 , H01L2224/11849 , H01L2224/13018 , H01L2224/13562 , H01L2224/13565 , H01L2224/80815 , H01L2224/81815 , H01L2924/01322 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2924/00012

摘要： A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.

摘要翻译： 半导体器件包括覆盖并电连接到焊盘区域的焊料凸块和形成在焊料凸块的至少一部分上的金属盖层。金属盖层的熔融温度大于焊料凸块的熔化温度。

2.

发明申请
COOLING MECHANISM FOR STACKED DIE PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：堆叠式包装的冷却机构及其制造方法

公开(公告)号：US20120061059A1

公开(公告)日：2012-03-15

申请号：US13033840

申请日：2011-02-24

申请人： Yi-Li HSIAO , Chen-Hua Yu , Da-Yuan Shih , Chih-Hang Tung , Chun Hui Yu

发明人： Yi-Li HSIAO , Chen-Hua Yu , Da-Yuan Shih , Chih-Hang Tung , Chun Hui Yu

IPC分类号： F28D15/00

CPC分类号： F28D15/02 , H01L23/34 , H01L23/473 , H01L25/0657 , H01L25/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06589 , H01L2924/00014 , H01L2924/1461 , H01L2924/15788 , H01L2924/00 , H01L2224/0401

摘要： An apparatus for cooling a stacked die package comprises a first die provided above a substrate; a second die above the first die; a cooling fluid in fluid communication with the first die and the second die, the cooling fluid for absorbing thermal energy from the first and the second die; a housing containing the first and second dies, the housing sealing the first and second dies from an environment, wherein the housing further includes a first opening and a second opening, the first and second openings being vertically displaced from one another; a conduit having one end connected to the first opening and the other end connected to the second opening, the conduit allowing the cooling liquid to circulate from the first opening to the second opening; a first temperature sensor being arranged to provide an output that is dependent on a local temperature at the first opening; and a second temperature sensor being arranged to provide an output that is dependent on a local temperature at the second opening, wherein the outputs of the first and second temperature sensors relative to each other are indicative of a level of the cooling fluid.

摘要翻译： 一种用于冷却堆叠的管芯封装的设备，包括设置在衬底上的第一管芯; 第一个模具上方的第二个模具; 与第一模具和第二模具流体连通的冷却流体，用于从第一模具和第二模具吸收热能的冷却流体; 壳体，其包含第一和第二模具，所述壳体将环境中的第一和第二模具密封，其中所述壳体还包括第一开口和第二开口，所述第一和第二开口彼此垂直移位; 导管，其一端连接到第一开口，另一端连接到第二开口，导管允许冷却液从第一开口循环到第二开口; 第一温度传感器被布置成提供依赖于第一开口处的局部温度的输出; 并且第二温度传感器被布置成提供取决于第二开口处的局部温度的输出，其中第一和第二温度传感器相对于彼此的输出指示冷却流体的水平。

3.

发明授权
End point detection in grinding 有权

公开(公告)号：US09960088B2

公开(公告)日：2018-05-01

申请号：US13290879

申请日：2011-11-07

申请人： Yi-Chao Mao , Jui-Pin Hung , Jing-Cheng Lin , Shin-Puu Jeng , Chen-Hua Yu

发明人： Yi-Chao Mao , Jui-Pin Hung , Jing-Cheng Lin , Shin-Puu Jeng , Chen-Hua Yu

IPC分类号： B24B49/10 , H01L21/66 , B24B37/013 , B24B7/22 , H01L23/31

CPC分类号： H01L22/26 , B24B7/228 , B24B37/013 , B24B49/10 , H01L22/12 , H01L23/3114 , H01L2924/0002 , H01L2924/00

摘要： A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the proceeding of the grinding process, wheel loadings of the grinding process are measured. The grinding process is stopped after the target wheel loading is reached. The method alternatively includes selecting a target reflectivity of wafer grinding processes, and performing a grinding process on a wafer. With a proceeding of the grinding process, reflectivities of a light reflected from a surface of the wafer are measured. The grinding process is stopped after one of the reflectivities reaches the target reflectivity.

4.

发明授权
Seal ring structure with improved cracking protection and reduced problems 有权
标题翻译：密封环结构具有改进的开裂保护和减少的问题

公开(公告)号：US08643147B2

公开(公告)日：2014-02-04

申请号：US11933931

申请日：2007-11-01

申请人： Shin-Puu Jeng , Shih-Hsun Hsu , Shang-Yun Hou , Hao-Yi Tsai , Chen-Hua Yu

发明人： Shin-Puu Jeng , Shih-Hsun Hsu , Shang-Yun Hou , Hao-Yi Tsai , Chen-Hua Yu

IPC分类号： H01L23/544

CPC分类号： H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00

摘要： An integrated circuit structure includes a lower dielectric layer; an upper dielectric layer over the lower dielectric layer; and a seal ring. The seal ring includes an upper metal line in the upper dielectric layer; a continuous via bar underlying and abutting the upper metal line, wherein the continuous via bar has a width greater than about 70 percent of a width of the upper metal line; a lower metal line in the lower dielectric layer; and a via bar underlying and abutting the lower metal line. The via bar has a width substantially less than a half of a width of the lower metal line.

摘要翻译： 集成电路结构包括下介电层; 在下介电层上的上电介质层; 和密封环。密封环包括在上介电层中的上金属线; 连续的通孔条，其下面并邻接上部金属线，其中所述连续通孔条具有大于所述上部金属线宽度的约70％的宽度; 下介电层中的下金属线; 以及位于下金属线下方并邻接的通孔条。通孔棒具有基本上小于下金属线宽度的一半的宽度。

5.

发明授权
Passivation layer for packaged chip 有权
标题翻译：封装芯片的钝化层

公开(公告)号：US08558229B2

公开(公告)日：2013-10-15

申请号：US13313747

申请日：2011-12-07

申请人： Shin-Puu Jeng , Wei-Cheng Wu , Shang-Yun Hou , Chen-Hua Yu , Tzuan-Horng Liu , Tzu-Wei Chiu , Kuo-Ching Hsu

发明人： Shin-Puu Jeng , Wei-Cheng Wu , Shang-Yun Hou , Chen-Hua Yu , Tzuan-Horng Liu , Tzu-Wei Chiu , Kuo-Ching Hsu

IPC分类号： H01L23/58

CPC分类号： H01L22/34 , G01R31/2884 , H01L21/76885 , H01L22/32 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/02126 , H01L2224/0401 , H01L2224/05001 , H01L2224/0554 , H01L2224/10126 , H01L2224/13005 , H01L2224/16225 , H01L2924/12044 , H01L2924/15311 , H01L2924/00

摘要： The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.

摘要翻译： 上述实施例提供了在封装的集成电路（IC）芯片上用测试焊盘在金属焊盘上形成金属凸块的机构。形成钝化层以覆盖测试焊盘和可能的金属焊盘部分。钝化层不覆盖远离测试焊盘区域和金属焊盘区域的表面。通过钝化层测试焊盘和金属焊盘部分的有限覆盖减少了形成在金属焊盘和金属凸块之间的UBM层的界面电阻。这种界面电阻的降低导致金属凸块的电阻降低。

6.

发明申请
Molding Chamber Apparatus and Curing Method 审中-公开

公开(公告)号：US20130087951A1

公开(公告)日：2013-04-11

申请号：US13270957

申请日：2011-10-11

申请人： Jing-Cheng Lin , Hsien-Wen Liu , Jui-Pin Hung , Shin-Puu Jeng , Chen-Hua Yu

发明人： Jing-Cheng Lin , Hsien-Wen Liu , Jui-Pin Hung , Shin-Puu Jeng , Chen-Hua Yu

IPC分类号： H05B6/64 , B29C35/08

CPC分类号： B29C35/0805 , B29C2035/0855 , H01L21/565 , H05B6/6491 , H05B6/806

摘要： An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component.

7.

发明申请
Method for Three Dimensional Integrated Circuit Fabrication 审中-公开
标题翻译：三维集成电路制作方法

公开(公告)号：US20130075892A1

公开(公告)日：2013-03-28

申请号：US13246553

申请日：2011-09-27

申请人： Jing-Cheng Lin , Weng-Jin Wu , Ying-Ching Shih , Jui-Pin Hung , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu

发明人： Jing-Cheng Lin , Weng-Jin Wu , Ying-Ching Shih , Jui-Pin Hung , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu

IPC分类号： H01L23/48 , H01L21/50

CPC分类号： H01L23/48 , H01L21/6835 , H01L24/94 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L2221/68327 , H01L2224/0401 , H01L2224/05009 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2224/97 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/351 , H01L2924/3511 , H01L2924/00012 , H01L2224/81 , H01L2924/00 , H01L2224/83

摘要： A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

摘要翻译： 一种用于制造三维集成电路的方法包括：提供其中多个半导体管芯安装在第一半导体管芯上的晶片堆叠，在第一半导体管芯的第一侧上形成模塑料层，其中多个半导体管芯被嵌入在模塑料层中。该方法还包括研磨第一半导体管芯的第二面直到多个通孔露出，将晶片堆叠附着到带框架上并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

8.

发明申请
Interconnect Structure for Wafer Level Package 有权
标题翻译：晶圆级封装的互连结构

公开(公告)号：US20130001776A1

公开(公告)日：2013-01-03

申请号：US13170973

申请日：2011-06-28

申请人： Chen-Hua Yu , Jing-Cheng Lin , Nai-Wei Liu , Jui-Pin Hung , Shin-Puu Jeng

发明人： Chen-Hua Yu , Jing-Cheng Lin , Nai-Wei Liu , Jui-Pin Hung , Shin-Puu Jeng

IPC分类号： H01L23/485 , H01L21/28

CPC分类号： H01L21/4853 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/78 , H01L23/3128 , H01L23/481 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/05008 , H01L2224/05569 , H01L2224/05572 , H01L2224/12105 , H01L2224/13022 , H01L2224/13025 , H01L2224/131 , H01L2224/13147 , H01L2224/73267 , H01L2224/94 , H01L2224/96 , H01L2924/00014 , H01L2924/01029 , H01L2924/0132 , H01L2924/014 , H01L2924/181 , H01L2224/19 , H01L2224/11 , H01L2224/03 , H01L2224/05552 , H01L2924/00 , H01L2224/214

摘要： A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.

摘要翻译： 封装包括具有基板的器件裸片。模塑料与基材的侧壁接触。金属焊盘在基板上。钝化层具有覆盖金属焊盘的边缘部分的部分。金属支柱已经过去并与金属垫接触。介电层位于钝化层的上方。由模塑料或聚合物形成的包装材料在电介质层的上面。电介质层包括位于钝化层和封装材料之间的底部，以及在金属柱的侧壁和封装材料的侧壁之间的侧壁部分。聚合物层在包装材料，模塑料和金属支柱之上。后钝化互连（PPI）延伸到聚合物层中。焊球在PPI上方，并通过PPI电耦合到金属焊盘。