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公开(公告)号:US08872345B2
公开(公告)日:2014-10-28
申请号:US13178079
申请日:2011-07-07
申请人: Chi-Chun Hsieh , Wei-Cheng Wu , Hsiao-Tsung Yen , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng
发明人: Chi-Chun Hsieh , Wei-Cheng Wu , Hsiao-Tsung Yen , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号: H01L23/48 , H01L21/283 , H01L21/74
CPC分类号: H01L23/481 , H01L21/743 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要: A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILD layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.
摘要翻译: 形成插入件的方法包括提供半导体衬底,该半导体衬底具有与前表面相对的前表面和后表面; 形成从所述前表面延伸到所述半导体衬底中的一个或多个穿硅通孔(TSV); 形成覆盖所述半导体衬底的前表面和所述一个或多个TSV的层间介电层(ILD)层; 以及在所述ILD层中形成互连结构,所述互连结构将所述一个或多个TSV电连接到所述半导体衬底。
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公开(公告)号:US08502338B2
公开(公告)日:2013-08-06
申请号:US12878803
申请日:2010-09-09
申请人: Hsiao-Tsung Yen , Hsien-Pin Hu , Chin-Wei Kuo , Sally Liu
发明人: Hsiao-Tsung Yen , Hsien-Pin Hu , Chin-Wei Kuo , Sally Liu
IPC分类号: H01L29/00
CPC分类号: H01L27/0296 , H01L21/76898 , H01L23/481 , H01L23/60 , H01L29/861 , H01L2223/6622 , H01L2224/13023 , H01L2224/13025 , H01L2224/13027 , H01L2224/131 , H01L2224/14181 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014
摘要: A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate.
摘要翻译: 一种器件包括第一导电类型的半导体衬底,其中半导体衬底包括与第一表面相对的第一表面和第二表面。 贯穿基板通孔(TSV)从半导体基板的第一表面延伸到第二表面。 与第一导电类型相反的第二导电类型的阱区域包围TSV,并且从半导体衬底的第一表面延伸到第二表面。
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公开(公告)号:US20120061795A1
公开(公告)日:2012-03-15
申请号:US12878803
申请日:2010-09-09
申请人: Hsiao-Tsung Yen , Hsien-Pin Hu , Chin-Wei Kuo , Sally Liu
发明人: Hsiao-Tsung Yen , Hsien-Pin Hu , Chin-Wei Kuo , Sally Liu
IPC分类号: H01L29/92 , H01L21/265
CPC分类号: H01L27/0296 , H01L21/76898 , H01L23/481 , H01L23/60 , H01L29/861 , H01L2223/6622 , H01L2224/13023 , H01L2224/13025 , H01L2224/13027 , H01L2224/131 , H01L2224/14181 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014
摘要: A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate.
摘要翻译: 一种器件包括第一导电类型的半导体衬底,其中半导体衬底包括与第一表面相对的第一表面和第二表面。 贯穿基板通孔(TSV)从半导体基板的第一表面延伸到第二表面。 与第一导电类型相反的第二导电类型的阱区域包围TSV,并且从半导体衬底的第一表面延伸到第二表面。
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公开(公告)号:US08471358B2
公开(公告)日:2013-06-25
申请号:US12791705
申请日:2010-06-01
申请人: Hsiao-Tsung Yen , Chin-Wei Kuo , Hsien-Pin Hu , Sally Liu , Ming-Fa Chen , Jhe-Ching Lu
发明人: Hsiao-Tsung Yen , Chin-Wei Kuo , Hsien-Pin Hu , Sally Liu , Ming-Fa Chen , Jhe-Ching Lu
IPC分类号: H01L27/08
CPC分类号: H01L23/5227 , H01F17/0013 , H01F27/2804 , H01L23/49822 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01322 , H01L2924/15311 , H01L2924/15321 , H01L2924/00 , H01L2224/0401
摘要: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.
摘要翻译: 根据实施例,半导体器件包括半导体管芯,插入件和将半导体管芯接合到插入件的导电凸块。 半导体管芯包括第一金属化层,第一金属化层包括第一导电图案。 插入器包括第二金属化层,并且第二金属化层包括第二导电图案。 一些导电凸块将第一导电图案电耦合到第二导电图案以形成线圈。 其他实施例考虑了线圈,电感器和/或变压器的其他配置,并考虑了制造方法。
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公开(公告)号:US08362591B2
公开(公告)日:2013-01-29
申请号:US12795734
申请日:2010-06-08
申请人: Hsiao-Tsung Yen , Hsien-Pin Hu , Jhe-Ching Lu , Chin-Wei Kuo , Ming-Fa Chen , Sally Liu
发明人: Hsiao-Tsung Yen , Hsien-Pin Hu , Jhe-Ching Lu , Chin-Wei Kuo , Ming-Fa Chen , Sally Liu
IPC分类号: H01L29/93
CPC分类号: H01L27/016 , H01L29/93
摘要: A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.
摘要翻译: 三维集成电路包括半导体衬底,其中衬底具有延伸穿过衬底的第一表面和第二表面的开口,并且其中第一表面和第二表面是与衬底相对的表面。 导电材料基本上填充衬底的开口以形成导电的通过衬底通孔(TSV)。 有源电路设置在衬底的第一表面上,电感器设置在衬底的第二表面上,并且TSV电耦合到有源电路和电感器。 三维集成电路可以包括由形成在基板的开口中的电介质层形成的变容二极管,使得导电材料邻近介电层设置,以及设置在TSV周围的杂质注入区域,使得介电层形成在 杂质注入区和TSV。
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公开(公告)号:US20110291232A1
公开(公告)日:2011-12-01
申请号:US12791705
申请日:2010-06-01
申请人: Hsiao-Tsung Yen , Chin-Wei Kuo , Hsien-Pin Hu , Sally Liu , Ming-Fa Chen , Jhe-Ching Lu
发明人: Hsiao-Tsung Yen , Chin-Wei Kuo , Hsien-Pin Hu , Sally Liu , Ming-Fa Chen , Jhe-Ching Lu
CPC分类号: H01L23/5227 , H01F17/0013 , H01F27/2804 , H01L23/49822 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01322 , H01L2924/15311 , H01L2924/15321 , H01L2924/00 , H01L2224/0401
摘要: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.
摘要翻译: 根据实施例,半导体器件包括半导体管芯,插入件和将半导体管芯接合到插入件的导电凸块。 半导体管芯包括第一金属化层,第一金属化层包括第一导电图案。 插入器包括第二金属化层,并且第二金属化层包括第二导电图案。 一些导电凸块将第一导电图案电耦合到第二导电图案以形成线圈。 其他实施例考虑了线圈,电感器和/或变压器的其他配置,并考虑了制造方法。
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公开(公告)号:US09923101B2
公开(公告)日:2018-03-20
申请号:US13615503
申请日:2012-09-13
申请人: Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Chewn-Pu Jou , Min-Chie Jeng
发明人: Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Chewn-Pu Jou , Min-Chie Jeng
CPC分类号: H01L29/94 , H01L22/34 , H01L23/481 , H01L23/585 , H01L27/0629 , H01L28/60 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.
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公开(公告)号:US08890222B2
公开(公告)日:2014-11-18
申请号:US13365303
申请日:2012-02-03
申请人: Hsiao-Tsung Yen , Yu-Ling Lin
发明人: Hsiao-Tsung Yen , Yu-Ling Lin
IPC分类号: H01L27/108 , H01L29/8605
CPC分类号: H01L27/10808 , H01L21/823475 , H01L23/5226 , H01L23/5228 , H01L23/528 , H01L27/0629 , H01L27/0802 , H01L27/10844 , H01L27/10897 , H01L28/20 , H01L29/0653 , H01L2924/0002 , H01L2924/00
摘要: A meander line resistor structure comprises a first resistor formed on a first active region, wherein the first resistor is formed by a plurality of first vias connected in series, a second resistor formed on a second active region, wherein the second resistor is formed by a plurality of second vias connected in series and a third resistor formed on the second active region, wherein the third resistor is formed by a plurality of third vias connected in series. The meander line resistor further comprises a first connector coupled between the first resistor and the second resistor.
摘要翻译: 弯曲线电阻器结构包括形成在第一有源区上的第一电阻器,其中第一电阻器由串联连接的多个第一通孔形成,第二电阻器形成在第二有源区上,其中第二电阻器由 串联连接的多个第二通孔和形成在第二有源区上的第三电阻器,其中第三电阻器由串联连接的多个第三通孔形成。 曲折线电阻器还包括耦合在第一电阻器和第二电阻器之间的第一连接器。
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公开(公告)号:US20140008773A1
公开(公告)日:2014-01-09
申请号:US13541937
申请日:2012-07-05
申请人: Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
发明人: Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号: H01L25/065 , H01L21/50
CPC分类号: H01Q1/38 , H01L23/66 , H01L25/0652 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2223/6677 , H01L2924/0002 , H01Q1/2283 , H01Q1/40 , H01Q7/00 , H01L2924/00
摘要: Some embodiments relate to a semiconductor module comprising an integrated antenna structure configured to wirelessly transmit signals. The integrated antenna structure has a lower metal layer and an upper metal layer. The lower metal layer is disposed on a lower die and is connected to a ground terminal. The upper metal layer is disposed on an upper die and is connected to a signal generator configured to generate a signal to be wirelessly transmitted. The upper die is stacked on the lower die and is connected to the lower die by way of an adhesion layer having one or more micro-bumps. By connecting the lower and upper die together by way of the adhesion layer, the lower and upper metal layers are separated from each other by a large spacing that provides for a good performance of the integrated antenna structure.
摘要翻译: 一些实施例涉及包括被配置为无线传输信号的集成天线结构的半导体模块。 集成天线结构具有下金属层和上金属层。 下金属层设置在下模上并连接到接地端子。 上金属层设置在上模上并连接到被配置为产生要无线传输的信号的信号发生器。 上模具堆叠在下模上,并通过具有一个或多个微凸块的粘合层连接到下模。 通过将粘合层连接在一起,下部和上部金属层彼此间隔开大间隔,从而提供了集成天线结构的良好性能。
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公开(公告)号:US08552812B2
公开(公告)日:2013-10-08
申请号:US12963701
申请日:2010-12-09
申请人: Hsiao-Tsung Yen , Yu-Ling Lin , Ying-Ta Lu , Chin-Wei Kuo , Ho-Hsiang Chen
发明人: Hsiao-Tsung Yen , Yu-Ling Lin , Ying-Ta Lu , Chin-Wei Kuo , Ho-Hsiang Chen
CPC分类号: H01L23/5227 , H01F17/0006 , H01F2017/0086 , H01L23/5223 , H01L2924/0002 , Y10T29/41 , H01L2924/00
摘要: An electronic device comprises first, second and third inductors connected in series and formed in a metal layer over a semiconductor substrate. The first and second inductors have a mutual inductance with each other. The second and third inductors having a mutual inductance with each other. A first capacitor has a first electrode connected to a first node. The first node is conductively coupled between the first and second inductors. A second capacitor has a second electrode connected to a second node. The second node is conductively coupled between the second and third inductors.
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