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37 条记录 (耗时 0.021 秒)

    Gated-varactors
    1.
    发明授权
    Gated-varactors 有权
    门控变容二极管

    公开(公告)号：US08273616B2

    公开(公告)日：2012-09-25

    申请号：US12708603

    申请日：2010-02-19

    申请人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Chin-Wei Kuo ,  Sally Liu

    发明人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Chin-Wei Kuo ,  Sally Liu

    IPC分类号： H01L21/00

    CPC分类号： H01L29/93 ,  H01L29/7391 ,  H01L29/94

    摘要： Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed.

    摘要翻译： 本发明的各种实施例提供了一种变容二极管结构，其取决于配置，可以提供基于反向偏置结电容器，沟道电容器和氧化物电容器中的一个或其组合的C-V特性。 结电容器通过反向偏置P +源极区域和N阱来形成。 在P +源极区域和N +漏极区域之间形成沟道电容，并且在栅极氧化物区域形成氧化物电容器。 取决于偏压栅极电压VG，源极电压VS和漏极电压VD的一个或组合，实施例可以利用上述电容器中的一个或组合。 还公开了在压控振荡器（VCO）中使用变容二极管的其它实施例。

    Filter using a waveguide structure
    2.
    发明授权
    Filter using a waveguide structure 有权
    使用波导结构滤波

    公开(公告)号：US08946832B2

    公开(公告)日：2015-02-03

    申请号：US12701170

    申请日：2010-02-05

    申请人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Chin-Wei Kuo

    发明人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Chin-Wei Kuo

    IPC分类号： H01L29/84 ,  H01P1/203

    CPC分类号： H01P1/20345

    摘要： A representative filter comprises a silicon-on-insulator substrate having a top surface, a metal shielding positioned above the top surface of the silicon-on-insulator substrate, and a band-pass filter device positioned above the metal shielding. The band-pass filter device includes a first port, a second port, and a coupling metal positioned between the first and second ports.

    摘要翻译： 代表性滤波器包括具有顶表面的绝缘体上硅衬底，位于绝缘体上硅衬底的顶表面上方的金属屏蔽以及位于金属屏蔽上方的带通滤波器器件。 带通滤波器装置包括位于第一和第二端口之间的第一端口，第二端口和耦合金属。

    Four-terminal gate-controlled LVBJTs
    3.
    发明授权
    Four-terminal gate-controlled LVBJTs 有权
    四端门控LVBJT

    公开(公告)号：US08115280B2

    公开(公告)日：2012-02-14

    申请号：US12715071

    申请日：2010-03-01

    申请人： Chia-Chung Chen ,  Shuo-Mao Chen ,  Chin-Wei Kuo ,  Sally Liu

    发明人： Chia-Chung Chen ,  Shuo-Mao Chen ,  Chin-Wei Kuo ,  Sally Liu

    IPC分类号： H01L29/735 ,  H01L29/732

    CPC分类号： H01L21/8224 ,  H01L27/0207 ,  H01L27/0821 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/0692 ,  H01L29/735

    摘要： An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.

    摘要翻译： 集成电路结构包括第一导电类型的阱区域，在阱区域上与第一导电类型相反的第二导电类型的发射极，在阱区域上的基本上环绕发射极的第二导电类型的集电极，以及 第一导电类型在阱区上的基极接触。 基座接触件通过收集器与发射器水平间隔开。 至少一个导电条水平地将发射器，集电器和基座接触件彼此分开间隔开。 电介质层直接位于至少一个导电带的下面并与其接触。

    Four-Terminal Gate-Controlled LVBJTs
    4.
    发明申请
    Four-Terminal Gate-Controlled LVBJTs 有权
    四端门控LVBJT

    公开(公告)号：US20100219504A1

    公开(公告)日：2010-09-02

    申请号：US12715071

    申请日：2010-03-01

    申请人： Chia-Chung Chen ,  Shuo-Mao Chen ,  Chin-Wei Kuo ,  Sally Liu

    发明人： Chia-Chung Chen ,  Shuo-Mao Chen ,  Chin-Wei Kuo ,  Sally Liu

    IPC分类号： H01L29/735

    CPC分类号： H01L21/8224 ,  H01L27/0207 ,  H01L27/0821 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/0692 ,  H01L29/735

    摘要： An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.

    摘要翻译： 集成电路结构包括第一导电类型的阱区域，在阱区域上与第一导电类型相反的第二导电类型的发射极，在阱区域上的基本上环绕发射极的第二导电类型的集电极，以及 第一导电类型在阱区上的基极接触。 基座接触件通过收集器与发射器水平间隔开。 至少一个导电条水平地将发射器，集电器和基座接触件彼此分开间隔开。 电介质层直接位于至少一个导电带的下面并与其接触。

    Slot-shielded coplanar strip-line compatible with CMOS processes
    5.
    发明授权
    Slot-shielded coplanar strip-line compatible with CMOS processes 有权
    与CMOS工艺兼容的插槽屏蔽共面带状线

    公开(公告)号：US09087840B2

    公开(公告)日：2015-07-21

    申请号：US12917285

    申请日：2010-11-01

    申请人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chin-Wei Kuo ,  Chewn-Pu Jou

    发明人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chin-Wei Kuo ,  Chewn-Pu Jou

    IPC分类号： H01L23/14 ,  H01L23/522 ,  H01L23/66 ,  H01L27/06

    CPC分类号： H01L23/5225 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/64 ,  H01L23/66 ,  H01L27/0629 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.

    摘要翻译： 带状线包括在衬底上延伸穿过多个电介质层的接地平面; 在基板上并在接地平面的一侧的信号线; 在信号线下方和第一金属层中的第一多个金属条，其中所述第一多个金属条彼此平行并且彼此间隔开; 以及信号线下方的第二多个金属条，并且在第一金属层上方的第二金属层中。 第二多个金属带垂直地与空间重叠。 第一多个金属条通过接地平面电耦合到第二多个金属条，并且不通过物理地接触第一多个金属条和第二多个金属条。

    Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes
    7.
    发明申请
    Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes 有权
    Slot-Shielded Coplanar Strip-line兼容CMOS工艺

    公开(公告)号：US20120104575A1

    公开(公告)日：2012-05-03

    申请号：US12917285

    申请日：2010-11-01

    申请人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chin-Wei Kuo ,  Chewn-Pu Jou

    发明人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chin-Wei Kuo ,  Chewn-Pu Jou

    IPC分类号： H01L23/14

    CPC分类号： H01L23/5225 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/64 ,  H01L23/66 ,  H01L27/0629 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.

    摘要翻译： 带状线包括在衬底上延伸穿过多个电介质层的接地平面; 在基板上并在接地平面的一侧的信号线; 在信号线下方和第一金属层中的第一多个金属条，其中所述第一多个金属条彼此平行并且彼此间隔开; 以及信号线下方的第二多个金属条，并且在第一金属层上方的第二金属层中。 第二多个金属带垂直地与空间重叠。 第一多个金属条通过接地平面电耦合到第二多个金属条，并且不通过物理地接触第一多个金属条和第二多个金属条。

    Integrated circuits and methods of forming the same
    9.
    发明授权
    Integrated circuits and methods of forming the same 有权
    集成电路及其形成方法

    公开(公告)号：US08362591B2

    公开(公告)日：2013-01-29

    申请号：US12795734

    申请日：2010-06-08

    申请人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Jhe-Ching Lu ,  Chin-Wei Kuo ,  Ming-Fa Chen ,  Sally Liu

    发明人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Jhe-Ching Lu ,  Chin-Wei Kuo ,  Ming-Fa Chen ,  Sally Liu

    IPC分类号： H01L29/93

    CPC分类号： H01L27/016 ,  H01L29/93

    摘要： A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.

    摘要翻译： 三维集成电路包括半导体衬底，其中衬底具有延伸穿过衬底的第一表面和第二表面的开口，并且其中第一表面和第二表面是与衬底相对的表面。 导电材料基本上填充衬底的开口以形成导电的通过衬底通孔（TSV）。 有源电路设置在衬底的第一表面上，电感器设置在衬底的第二表面上，并且TSV电耦合到有源电路和电感器。 三维集成电路可以包括由形成在基板的开口中的电介质层形成的变容二极管，使得导电材料邻近介电层设置，以及设置在TSV周围的杂质注入区域，使得介电层形成在 杂质注入区和TSV。