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    Chip package and method for forming the same
    1.
    发明授权
    Chip package and method for forming the same 有权
    芯片封装及其形成方法

    公开(公告)号：US08362515B2

    公开(公告)日：2013-01-29

    申请号：US13081346

    申请日：2011-04-06

    申请人： Chia-Ming Cheng ,  Chien-Hung Liu

    发明人： Chia-Ming Cheng ,  Chien-Hung Liu

    IPC分类号： H01L33/00

    CPC分类号： H01L23/49805 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/481 ,  H01L23/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2924/0002 ,  H01L2924/01021 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05552

    摘要： An embodiment of the invention provides a chip package which includes a substrate having an upper surface and a lower surface and having at least a side surface, and at least a trench extending from the upper surface towards the lower surface and extending from the side surface towards an inner portion of the substrate, wherein a width of the trench near the upper surface is not equal to a width of the trench near the lower surface, and at least an insulating layer located on a sidewall of the trench, and at least a conducting pattern located on the insulating layer, wherein the side surface is separated from the conducting pattern in the trench by a predetermined distance such that a portion of the insulating layer is exposed, and at least a conducting region electrically connected to the conducting pattern.

    摘要翻译： 本发明的一个实施例提供了一种芯片封装，其包括具有上表面和下表面的基板，并且至少具有一个侧表面，以及至少一个从上表面向下表面延伸并且从侧表面向着 衬底的内部部分，其中靠近上表面的沟槽的宽度不等于下表面附近的沟槽的宽度，以及至少位于沟槽的侧壁上的绝缘层，并且至少导电 位于所述绝缘层上，其中所述侧表面与所述沟槽中的导电图案分离预定距离，使得所述绝缘层的一部分露出，以及至少导电区域电连接到所述导电图案。

    Chip package
    2.
    发明授权
    Chip package 有权
    芯片封装

    公开(公告)号：US08384174B2

    公开(公告)日：2013-02-26

    申请号：US13070375

    申请日：2011-03-23

    申请人： Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

    发明人： Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

    IPC分类号： H01L31/0203

    CPC分类号： H01L31/02164 ,  H01L27/14618 ,  H01L33/486 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/13

    摘要： A chip package includes: a substrate having a first and a second surfaces; an optical device on the first surface; a conducting layer on the second surface; a passivation layer on the second surface and the conducting layer, wherein the passivation layer has an opening exposing the conducting layer; a conducting bump on the second surface and having a bottom and an upper portions, wherein the bottom portion is disposed in the opening and electrically contacts the conducting layer, and the upper portion is located outside of the opening and extends along a direction away from the opening; a recess extending from a surface of the conducting bump toward an inner portion of the conducting bump; and a light shielding layer on the second surface, extending under the upper portion, and partially located in the recess and overlapping a portion of the conducting bump.

    摘要翻译： 芯片封装包括：具有第一和第二表面的衬底; 第一表面上的光学装置; 第二表面上的导电层; 所述第二表面上的钝化层和所述导电层，其中所述钝化层具有暴露所述导电层的开口; 在第二表面上具有导电凸起并具有底部和上部，其中底部设置在开口中并与导电层电接触，并且上部位于开口的外侧，并沿远离 开口 从所述导电凸块的表面延伸到所述导电凸块的内部的凹部; 以及在所述第二表面上的遮光层，在所述上部下方延伸，并且部分地位于所述凹部中并与所述导电凸块的一部分重叠。

    CHIP PACKAGE
    3.
    发明申请
    CHIP PACKAGE 有权
    芯片包装

    公开(公告)号：US20110233770A1

    公开(公告)日：2011-09-29

    申请号：US13070375

    申请日：2011-03-23

    申请人： Hsin-Chih CHIU ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

    发明人： Hsin-Chih CHIU ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

    IPC分类号： H01L23/498

    CPC分类号： H01L31/02164 ,  H01L27/14618 ,  H01L33/486 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/13

    摘要： A chip package includes: a substrate having a first and a second surfaces; an optical device on the first surface; a conducting layer on the second surface; a passivation layer on the second surface and the conducting layer, wherein the passivation layer has an opening exposing the conducting layer; a conducting bump on the second surface and having a bottom and an upper portions, wherein the bottom portion is disposed in the opening and electrically contacts the conducting layer, and the upper portion is located outside of the opening and extends along a direction away from the opening; a recess extending from a surface of the conducting bump toward an inner portion of the conducting bump; and a light shielding layer on the second surface, extending under the upper portion, and partially located in the recess and overlapping a portion of the conducting bump.

    摘要翻译： 芯片封装包括：具有第一和第二表面的衬底; 第一表面上的光学装置; 第二表面上的导电层; 所述第二表面上的钝化层和所述导电层，其中所述钝化层具有暴露所述导电层的开口; 在第二表面上具有导电凸起并具有底部和上部，其中底部设置在开口中并与导电层电接触，并且上部位于开口的外侧，并沿远离 开口 从所述导电凸块的表面延伸到所述导电凸块的内部的凹部; 以及在所述第二表面上的遮光层，在所述上部下方延伸，并且部分地位于所述凹部中并与所述导电凸块的一部分重叠。

    Linear Actuator Capable of Measuring Distance
    6.
    发明申请
    Linear Actuator Capable of Measuring Distance 审中-公开
    具有测量距离的线性致动器

    公开(公告)号：US20160230861A1

    公开(公告)日：2016-08-11

    申请号：US14673795

    申请日：2015-03-30

    申请人： Chia-Ming Cheng

    发明人： Chia-Ming Cheng

    IPC分类号： F16H25/20

    CPC分类号： F16H25/2015 ,  F16H2025/2034 ,  F16H2025/2075

    摘要： A linear actuator includes an actuator including a housing, a power drive mounted at one end of the housing, a screw rod axially disposed in the housing, a connection member connected between the screw rod and the power drive, a sliding block threaded onto the screw rod, and a push rod affixed to the sliding block and extending out of the housing, and a resistance scale including a resistance substrate affixed to an inner wall of the housing at an inner bottom side and a electric brush affixed to a bottom side of the sliding block and kept in contact with the resistance substrate.

    摘要翻译： 线性致动器包括致动器，其包括壳体，安装在壳体的一端的动力驱动器，轴向设置在壳体中的螺杆，连接在螺杆和动力驱动器之间的连接构件，螺纹连接到螺钉上的滑动块 杆和固定在滑动块上并延伸出壳体的推杆，以及包括固定在内底侧的壳体内壁上的电阻基板和固定在壳体的底侧的电刷的电阻标尺 滑块并与电阻基板保持接触。

    Photographic system
    7.
    发明授权
    Photographic system 有权
    摄影系统

    公开(公告)号：US08849014B2

    公开(公告)日：2014-09-30

    申请号：US13225682

    申请日：2011-09-06

    申请人： Chia-Ming Cheng

    发明人： Chia-Ming Cheng

    IPC分类号： G06K9/00 ,  G06K9/62 ,  G06K9/32 ,  G06T15/20 ,  G06K9/60 ,  G06T17/00 ,  H04N13/00

    CPC分类号： G06K9/60 ,  G06T15/20 ,  G06T17/00 ,  H04N13/111

    摘要： A photographic system for generating photos is provided. The photographic system comprises a photo composition unit, and a photo synthesizer. The photo composition unit is capable of determining an extracted view from a three dimensional (3D) scene. The photo synthesizer, coupled to the photo composition unit, is capable of synthesizing an output photo according to the extracted view.

    摘要翻译： 提供了一种用于生成照片的摄影系统。 照相系统包括照相组合单元和照相合成器。 该照片合成单元能够从三维（3D）场景确定提取的视图。 耦合到照相合成单元的照相合成器能够根据提取的视图合成输出照片。

    Chip package and fabrication method thereof
    8.
    发明授权
    Chip package and fabrication method thereof 有权
    芯片封装及其制造方法

    公开(公告)号：US08637970B2

    公开(公告)日：2014-01-28

    申请号：US12855447

    申请日：2010-08-12

    申请人： Chia-Lun Tsai ,  Chia-Ming Cheng ,  Long-Sheng Yeou

    发明人： Chia-Lun Tsai ,  Chia-Ming Cheng ,  Long-Sheng Yeou

    IPC分类号： H01L21/301 ,  H01L21/302

    CPC分类号： H01L21/78 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00825 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2203/0118

    摘要： An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

    摘要翻译： 本发明的实施例涉及一种芯片封装及其制造方法，其包括芯片保护层或附加的蚀刻停止层，以覆盖导电焊盘，以防止切割残留物损坏或划伤导电焊盘。 根据另一个实施例，当蚀刻结构蚀刻区域和硅衬底上的金属间电介质层时，可以使用芯片保护层，其上形成的附加蚀刻停止层或具有导电焊盘或其组合的金属蚀刻停止层， 形成随后的半导体制造工艺的开口。

    Dual CPU and heat dissipating structure thereof
    9.
    发明授权
    Dual CPU and heat dissipating structure thereof 有权
    双CPU和散热结构

    公开(公告)号：US08295050B2

    公开(公告)日：2012-10-23

    申请号：US12940611

    申请日：2010-11-05

    申请人： Hui-Hsuan Chuang ,  Chia-Ming Cheng

    发明人： Hui-Hsuan Chuang ,  Chia-Ming Cheng

    IPC分类号： H05K7/20

    CPC分类号： G06F1/20 ,  H01L23/467 ,  H01L2924/0002 ,  H05K7/20154 ,  H01L2924/00

    摘要： A dual CPU and its heat dissipating structure are applied to a heat dissipating module installed on a dual-CPU computer device, and CPUs are arranged alternately with each other on a motherboard, and the heat dissipating modules are installed at positions of the CPUs, such that the alternately arranged heat dissipating modules can prevent interferences by external cold air, and a heat source produced by the CPUs can be conducted and dissipated to the outside to prevent the heat source form remaining at the surrounding of the CPUs and related components installed on the motherboard to achieve an excellent heat dissipating efficiency.

    摘要翻译： 将双CPU及其散热结构应用于安装在双CPU计算机设备上的散热模块，并且CPU在主板上彼此交替布置，并且散热模块安装在CPU的位置，例如 交替布置的散热模块可以防止外部冷空气的干扰，并且由CPU产生的热源可以被传导并消散到外部，以防止残留在CPU周围的热源形式和安装在其上的相关部件 主板实现了出色的散热效率。

    Chip package and method for forming the same
    10.
    发明授权
    Chip package and method for forming the same 有权
    芯片封装及其形成方法

    公开(公告)号：US08431946B2

    公开(公告)日：2013-04-30

    申请号：US13114750

    申请日：2011-05-24

    申请人： Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

    发明人： Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

    IPC分类号： H01L33/00

    CPC分类号： H01L27/14618 ,  H01L31/048 ,  H01L2224/13 ,  H01L2933/0066 ,  Y02E10/50

    摘要： An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optical device disposed on the first surface; a conducting pad disposed on the first surface; a first alignment mark formed on the first surface; and a light shielding layer disposed on the second surface and having a second alignment mark, wherein the second alignment mark corresponds to the first alignment mark.

    摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 设置在所述第一表面上的光学装置; 设置在所述第一表面上的导电垫; 形成在第一表面上的第一对准标记; 以及遮光层，其设置在所述第二表面上并且具有第二对准标记，其中所述第二对准标记对应于所述第一对准标记。