公开(公告)号：US20050284656A1

公开(公告)日：2005-12-29

申请号：US11157827

申请日：2005-06-22

申请人： Chikara Shimada ,  Satoshi Torii

发明人： Chikara Shimada ,  Satoshi Torii

IPC分类号： B23K1/00 ,  B23K31/00 ,  H05K3/34

CPC分类号： H05K3/3468 ,  B23K1/0016 ,  B23K2101/42 ,  H05K3/3447 ,  H05K3/3452 ,  H05K2201/09063 ,  H05K2203/0557 ,  H05K2203/1178

摘要： The invention provides a printed circuit board to be subjected to dip soldering process using a dip soldering jig, the board capable of discharging gases generated by the volatilization of flux thereby preventing solder defects, and a method for manufacturing the printed circuit board. Gas venting holes 12 are formed in areas adjacent to lead wire welding components 11 on the forward side of the feeding direction of the printed circuit board in the dip soldering process (board feeding direction 13) and within the area of an opening 23 formed to the dip soldering jig 20. Thereby, gases generated during the dip soldering process are discharged efficiently.

摘要翻译： 本发明提供一种使用浸焊夹具进行浸焊工艺的印刷电路板，该板能够排出通过焊剂挥发产生的气体，从而防止焊料缺陷，以及制造印刷电路板的方法。 在浸渍焊接工艺（板材进给方向13）中，在印刷电路板的进给方向的前侧上的引线焊接部件11的相邻区域形成有排气孔12， 浸焊夹具20。 因此，在浸焊过程中产生的气体被有效地排出。

公开(公告)号：US07505328B1

公开(公告)日：2009-03-17

申请号：US11504254

申请日：2006-08-14

申请人： Satoshi Torii

发明人： Satoshi Torii

IPC分类号： G11C16/00

CPC分类号： G11C16/3418

摘要： Embodiments of the present invention disclose a method of utilizing a flash memory array to decrease programming time while maintaining sufficient read speeds. An array of cells is programmed and read in pages that are oriented in the column direction, parallel to the bit lines in the array. An erased cell in the present invention is a cell in the “off” state. According to the present invention a cell is programmed by lowering the threshold voltage of the cell, thereby turning the cell “on.” An array of cells is programmed read in a sector-by-sector method, wherein a sector consists of units situated diagonally adjacent to each other, and a unit consists of multiple parallel column-oriented pages.

摘要翻译： 本发明的实施例公开了一种利用闪存阵列来减少编程时间同时保持足够的读取速度的方法。 单元格阵列被编程和读取在与列方向相对齐的页面上，与阵列中的位线平行。 本发明中的擦除单元是处于“关闭”状态的单元。 根据本发明，通过降低电池的阈值电压来编程电池，从而使电池“接通”。 单元阵列以逐扇区方式被读取，其中扇区由彼此对角地相邻的单元组成，并且单元由多个平行的列为列的页组成。

公开(公告)号：US07416940B1

公开(公告)日：2008-08-26

申请号：US11418352

申请日：2006-05-03

申请人： Satoshi Torii ,  Hidehiko Shiraiwa ,  Youseok Suh ,  Lei Xue

发明人： Satoshi Torii ,  Hidehiko Shiraiwa ,  Youseok Suh ,  Lei Xue

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： Methods for fabricating a flash memory device are provided. A method comprises forming a plurality of gate stacks overlying a substrate. Each gate stack comprises a charge trapping layer and a control gate. The control gate is a first distance from the substrate. Adjacent gate stacks are a second distance apart. A cell spacer material layer is deposited and is etched to form a spacer about sidewalls of each gate stack. A source/drain impurity doped region is formed adjacent a first gate stack and a last gate stack. The first distance and the second distance are such that, when a voltage is applied to a gate stack during a READ operation, a fringing field is created between the control gate of the gate stack and the substrate and is sufficient to invert a portion of the substrate between the gate stack and an adjacent gate stack.

摘要翻译： 提供了制造闪速存储器件的方法。 一种方法包括形成覆盖衬底的多个栅叠层。 每个栅极堆叠包括电荷捕获层和控制栅极。 控制栅极是离基板的第一距离。 相邻的门堆叠是第二个距离。 沉积电池间隔物材料层并被蚀刻以形成围绕每个栅极叠层的侧壁的间隔物。 在第一栅极堆叠和最后一个栅极堆叠附近形成源极/漏极杂质掺杂区域。 第一距离和第二距离使得当在读取操作期间将电压施加到栅极堆叠时，在栅极堆叠的控制栅极和衬底之间产生边缘场，并且足以将一部分 栅极堆叠和相邻栅极堆叠之间的衬底。

公开(公告)号：US20070175659A1

公开(公告)日：2007-08-02

申请号：US11655877

申请日：2007-01-22

申请人： Satoshi Torii

发明人： Satoshi Torii

IPC分类号： H05K1/16

CPC分类号： H05K1/111 ,  H05K3/3468 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K2203/046 ,  Y02P70/611

摘要： Disclosed herein is a printed circuit board that allows a wiring pattern to be resistant to noise while maintaining solderability even in the case where a wiring pattern is drawn out from the lower part of a QFP. A printed circuit board on which a QFP is mounted by dip soldering is provided with two separate solder flow lands formed between a front soldering land group and a rear soldering land group and a wiring pattern formed between the two separate solder flow lands, wherein the wiring pattern is a land having a width of not less than 0.3 mm, and a space between the wiring pattern and the solder flow lands is not less than 0.4 mm nor more than 0.8 mm.

摘要翻译： 这里公开了一种印刷电路板，即使在从QFP的下部引出布线图案的情况下，也能够在保持可焊性的同时，使布线图案耐噪声化。 通过浸焊在其上安装有QFP的印刷电路板设置有形成在前焊接组和后焊盘组之间的两个单独的焊料流动台面和形成在两个分离的焊料焊盘之间的布线图案，其中布线 图案是具有不小于0.3mm的宽度的焊盘，并且布线图案和焊料流焊台之间的间隔不小于0.4mm，也不大于0.8mm。

公开(公告)号：US07196008B1

公开(公告)日：2007-03-27

申请号：US11087793

申请日：2005-03-23

申请人： Hidehiko Shiraiwa ,  Satoshi Torii ,  Jaeyong Park ,  Joong Jeon

发明人： Hidehiko Shiraiwa ,  Satoshi Torii ,  Jaeyong Park ,  Joong Jeon

IPC分类号： H01L21/44

CPC分类号： H01L21/76829 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： For fabricating a memory device, spacers are formed to sides of word-line gates. In addition, aluminum oxide is formed as one of a liner layer or a cover layer to the spacers. The aluminum oxide has a chemical composition of Al2O3 for example. Such aluminum oxide may be used as an etch stop layer in a periphery region, a metal silicide block, and a hydrogen block for enhanced performance of the memory device.

摘要翻译： 为了制造存储器件，在字线栅极的侧面形成间隔物。 此外，氧化铝形成为间隔物的衬垫层或覆盖层之一。 氧化铝具有例如Al 2 O 3 N 3的化学组成。 这种氧化铝可以用作外围区域中的蚀刻停止层，金属硅化物块和氢块，以增强存储器件的性能。

公开(公告)号：US07167398B1

公开(公告)日：2007-01-23

申请号：US11062641

申请日：2005-02-23

申请人： Zhizheng Liu ,  Satoshi Torii ,  Mark Randolph ,  Yi He

发明人： Zhizheng Liu ,  Satoshi Torii ,  Mark Randolph ,  Yi He

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/14 ,  H01L29/66833 ,  H01L29/7923

摘要： A method erases a memory cell of a semiconductor device that includes a group of memory cells. Each memory cell includes a group of storage regions. The method includes determining that each storage region of the group of storage regions of a first memory cell is to be erased and erasing the group of storage regions of the first memory cell via a single hot hole injection process.

摘要翻译： 一种方法擦除包括一组存储单元的半导体器件的存储单元。 每个存储单元包括一组存储区域。 该方法包括：通过单个热孔注入处理确定要擦除第一存储器单元组的存储区域的每个存储区域并擦除第一存储单元的存储区域组。

公开(公告)号：US20060240617A1

公开(公告)日：2006-10-26

申请号：US11113508

申请日：2005-04-25

申请人： Satoshi Torii

发明人： Satoshi Torii

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115

摘要： Methods 500 and 550 are disclosed for fabricating an array source line structure in a wafer of a NAND flash memory device. One method aspect 500 comprises forming 510 a first oxide 610 and a nitride layer 611 of an ONO stack 620 over a substrate 604 and an STI 409 or 136 of the wafer 602 and 102, respectively, for example, then implanting 512 an N+ ion species through the stack 620 into a source line region 606 of the wafer 602. The method 500 further comprises forming 514 a second oxide layer 612 of the ONO stack 620 over the nitride layer 611 and forming an alumina layer 622 over the completed ONO stack 620 of the wafer 602, removing the ONOA stack (620 and 622) and forming 514 a gate oxide layer in the periphery region (not shown), then etching 516 an opening 626 in the ONOA stack 620 in an array source line region 606 of the wafer 602, for example, using a local interconnect mask. The method 500, also includes cleaning 518 the wafer and forming a polysilicon layer 628 over the wafer 602, and selectively etching 520 the polysilicon layer 628 and etching 522 the alumina layer 622 to concurrently form wordline 130 and select drain gate structures 124 in bitline contact regions (605, 608), and select source gate 116 structures and array source line structures 634 in source line regions 606. Method 500 further includes implanting 522 an N− dopant ion species, for example, an MDD material in openings of source/drain regions 106 formed in the wafer 602. The method 500 also comprises forming 524 sidewall spacers in bitline contact regions 605 and source line contact regions 606, implanting 526 an array ion species in the bitline contact regions 605, and finally, forming a silicide layer 654 in the polysilicon layer 604 in a core region to form a conductive layer for gate (116, 124), bitline 110, wordline 130, the select gate 116, and the source line structure contacts 132. Thus, the method 500 permits concurrent formation of the word lines 130, select gates 116, 124 and the array source lines 112 simultaneously to simplify and reduce the cost of the process, and to improve the yield without etching into the STI 409 or the use of a local interconnect structure.

公开(公告)号：US07113431B1

公开(公告)日：2006-09-26

申请号：US11091982

申请日：2005-03-29

申请人： Darlene Hamilton ,  Alykhan Madhani ,  Fatima Bathul ,  Satoshi Torii

发明人： Darlene Hamilton ,  Alykhan Madhani ,  Fatima Bathul ,  Satoshi Torii

IPC分类号： G11C16/14

CPC分类号： G11C16/3422 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/14 ,  G11C16/3418

摘要： The present invention pertains to a technique for erasing bits in a dual bit memory in a manner that maintains complementary bit disturb control of bit-pairs of memory cells wherein each bit of the dual bit memory cell can be programmed to multiple levels. One exemplary method comprises providing a word of memory cells after an initial erasure and programming of the bits of the word to one or more of the higher program levels. A disturb level is determined for each of the bit-pairs of the word. A combined disturb level is then computed that is representative of the individual disturb levels. A pattern of drain voltages is then applied to the word for a number of program passes until a target pattern is stored in the word of memory cells based on the combined disturb level and the unprogrammed bit of the bit-pairs is erased to a single program level. In this manner the present invention compensates for the disturbance level that exists between the complementary bit-pairs of the word, improves the Vt distribution at the program level of the erased state and thereby improves the accuracy of subsequent higher level programming operations and mitigates false or erroneous reads of the states of such program levels.

摘要翻译： 本发明涉及一种在双位存储器中擦除比特的技术，该技术维持存储器单元的比特对的互补位干扰控制，其中双比特存储单元的每个比特可被编程为多个级别。 一个示例性方法包括在初始擦除之后提供一个单词的存储单元，并将该单词的位编程到一个或多个较高程序级。 为单词的每个位对确定干扰级别。 然后计算代表各个干扰级别的组合干扰级别。 然后将漏极电压的模式施加到多个程序遍的字，直到目标模式基于组合的干扰电平存储在存储器单元的字中，并且位对的未编程位被擦除到单个程序 水平。 以这种方式，本发明补偿存在于字的互补位对之间的干扰电平，改善了擦除状态的程序级的Vt分布，从而提高了后续更高级编程操作的准确性，并减轻了错误或 错误地读取这些程序级别的状态。

公开(公告)号：US08507971B2

公开(公告)日：2013-08-13

申请号：US12187276

申请日：2008-08-06

申请人： Satoshi Torii

发明人： Satoshi Torii

IPC分类号： H01L29/76 ,  H01L31/119

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513

摘要： The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for increased process margins. Specifically, in one embodiment, each of the memory cells in the array of memory cells includes a source, a control gate, and a drain, and is capable of storing at least one bit. The array of memory cells further includes word lines that are coupled to control gates of memory cells. The word lines are arranged in rows in the array. In addition, the array comprises bit lines coupled to source and drains of memory cells. The bit lines are arranged in columns in the array. Also, the array comprises at least one row of bit line contacts for providing electrical conductivity to the bit lines. Further, the array comprises shallow trench isolation (STI) regions separating each of the bit lines along the row of bit line contacts.

摘要翻译： 本发明提供了一种用于非易失性存储器的装置和方法，该装置和方法包括在位线之间的浅沟槽隔离（STI）区域的至少一个存储单元阵列，用于增加工艺裕度。 具体地，在一个实施例中，存储单元阵列中的每个存储单元包括源极，控制栅极和漏极，并且能够存储至少一个位。 存储单元阵列还包括耦合到存储器单元的控制栅极的字线。 字线在数组中排成行。 此外，阵列包括耦合到存储器单元的源极和漏极的位线。 位线排列在数组中的列中。 而且，该阵列包括用于向位线提供导电性的至少一行位线触点。 此外，阵列包括沿着位线触点行分隔每个位线的浅沟槽隔离（STI）区域。

公开(公告)号：US08400828B2

公开(公告)日：2013-03-19

申请号：US13435901

申请日：2012-03-30

申请人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

发明人： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

IPC分类号： G11C16/04

CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.