公开(公告)号：US20110181245A1

公开(公告)日：2011-07-28

申请号：US12728288

申请日：2010-03-22

申请人： Chin-Long Wey ,  Chun-Ming Huang ,  Shih-Lun Chen ,  Chi-Sheng Lin ,  Ting-Hsu Chien ,  Jiann-Jenn Wang

发明人： Chin-Long Wey ,  Chun-Ming Huang ,  Shih-Lun Chen ,  Chi-Sheng Lin ,  Ting-Hsu Chien ,  Jiann-Jenn Wang

IPC分类号： H02J7/00

CPC分类号： H02J7/0016 ,  H02J7/0019 ,  H02J7/0024 ,  Y02T10/7055

摘要： The present invention discloses a unitized charging and discharging battery management system and a programmable battery management module thereof The unitized charging and discharging battery management system includes a smart battery module and a programmable battery management module, which has a universal loop and a control unit. The smart battery module has at least two smart batteries which are electrically connected by a plurality of switches and circuits of the universal loop to form a charging/discharging loop in series/parallel. The control unit monitors the charging and discharging status of the smart batteries to turn on or off the switches accordingly, so as to manage the smart batteries, thereby enhancing the overall power efficacy of the smart battery module. Besides, the service life of the smart battery module is also prolonged due to the simultaneous charging and discharging capability.

摘要翻译： 本发明公开了一种单元化充放电电池管理系统及其可编程电池管理模块。该单元化充放电电池管理系统包括智能电池模块和可编程电池管理模块，其具有通用回路和控制单元。 智能电池模块具有至少两个智能电池，其通过多个开关和通用回路的电路电连接以形成串/并联的充电/放电回路。 控制单元监视智能电池的充电和放电状态，以相应地打开或关闭开关，以便管理智能电池，从而提高智能电池模块的整体功率效率。 此外，智能电池模块的使用寿命也由于同时的充放电能力而延长。

公开(公告)号：US20110188210A1

公开(公告)日：2011-08-04

申请号：US12752345

申请日：2010-04-01

申请人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

发明人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

IPC分类号： H05K1/14 ,  H05K7/00

CPC分类号： H05K1/14 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K7/00

摘要： A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

摘要翻译： 提供了通过堆叠多个芯片模块形成的三维SoC结构。 三维SoC结构包括至少两个垂直SoC模块和至少一个连接器模块，其中每个连接器模块电连接两个垂直SoC模块。 每个垂直SoC模块通过垂直堆叠至少两个芯片模块构成。 每个芯片模块包括模块电路板和至少一个预设元件。 在每个模块电路板中形成凹部，并设置有用于与相应的至少一个预设元件电连接的第一连接接口。 至少两个垂直SoC模块通过连接器模块连接，形成具有多种功能的三维SoC结构。 此外，形成在模块电路板中的凹部为预设元件提供有效的散热路径。

公开(公告)号：US20100315131A1

公开(公告)日：2010-12-16

申请号：US12495107

申请日：2009-06-30

申请人： Chi Sheng Lin ,  Ting-Hsu Chien ,  Chin-Long Wey ,  Chun-Ming Huang ,  Ying-Zong Juang

发明人： Chi Sheng Lin ,  Ting-Hsu Chien ,  Chin-Long Wey ,  Chun-Ming Huang ,  Ying-Zong Juang

IPC分类号： H03B19/00

CPC分类号： H03L7/183 ,  H03K23/425 ,  H03L7/0802

摘要： A programmable frequency divider with a full dividing range includes a plurality of cascaded 2/1 frequency dividers. Each of the 2/1 frequency dividers has a first input node, a first output node, a second input node, a second output node and a third input node. The first input node receives a first clock signal divided by the 2/1 frequency divider and outputted as a second clock signal through the first output node. A second logical signal is generated according to the second clock signal, the first clock signal and a first logical signal received from the second input node. The 2/1 frequency divider selectively switches to perform a divide-by-two or divide-by-one operation according to the second logical signal and a first divisor signal received from the third input nodes. The programmable frequency divider provides the full dividing range as the result of utilizing various divisor of the 2/1 frequency divider.

摘要翻译： 具有全分频范围的可编程分频器包括多个级联的2/1分频器。 2/1分频器中的每一个具有第一输入节点，第一输出节点，第二输入节点，第二输出节点和第三输入节点。 第一输入节点接收由2/1分频器分频的第一时钟信号，并通过第一输出节点作为第二时钟信号输出。 根据第二时钟信号，第一时钟信号和从第二输入节点接收的第一逻辑信号产生第二逻辑信号。 2/1分频器选择性地切换以根据第二逻辑信号和从第三输入节点接收的第一除数信号执行二分频或一分频操作。 作为使用2/1分频器的各种除数的结果，可编程分频器可提供完整的分频范围。

公开(公告)号：US08199510B2

公开(公告)日：2012-06-12

申请号：US12685723

申请日：2010-01-12

申请人： Chun-Ming Huang ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chin-Long Wey ,  Chi-Shi Chen ,  Chi-Sheng Lin

发明人： Chun-Ming Huang ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chin-Long Wey ,  Chi-Shi Chen ,  Chi-Sheng Lin

IPC分类号： H05K7/20

CPC分类号： H05K7/20 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H05K1/0272 ,  H05K1/144 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/064 ,  H05K2201/09063 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/2018 ,  H05K2203/1572

摘要： A multi-layer system-on-chip (SoC) module structure is provided. The multi-layer SoC module structure includes at least two circuit board module layers and at least one connector module layer. Each connector module layer is sandwiched between and thus electrically connects two circuit board module layers such that the SoC module structure is formed by stacking. Each circuit board module layer is composed of at least one circuit board module while each connector module layer is composed of at least one connector module. Hence, the SoC module structure can be manufactured as a three-dimensional structure, thus allowing highly flexible connections within the SoC module structure.

摘要翻译： 提供了多层片上系统（SoC）模块结构。 多层SoC模块结构包括至少两个电路板模块层和至少一个连接器模块层。 每个连接器模块层夹在两个电路板模块层之间并由此电连接，使得SoC模块结构通过堆叠形成。 每个电路板模块层由至少一个电路板模块组成，而每个连接器模块层由至少一个连接器模块组成。 因此，SoC模块结构可以制造为三维结构，从而允许SoC模块结构内的高度灵活的连接。

公开(公告)号：US20110096506A1

公开(公告)日：2011-04-28

申请号：US12685723

申请日：2010-01-12

申请人： Chun-Ming Huang ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chin-Long Wey ,  Chi-Shi Chen ,  Chi-Sheng Lin

发明人： Chun-Ming Huang ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chin-Long Wey ,  Chi-Shi Chen ,  Chi-Sheng Lin

IPC分类号： H05K7/20 ,  H05K7/00

CPC分类号： H05K7/20 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H05K1/0272 ,  H05K1/144 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/064 ,  H05K2201/09063 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/2018 ,  H05K2203/1572

摘要： A multi-layer system-on-chip (SoC) module structure is provided. The multi-layer SoC module structure includes at least two circuit board module layers and at least one connector module layer. Each connector module layer is sandwiched between and thus electrically connects two circuit board module layers such that the SoC module structure is formed by stacking. Each circuit board module layer is composed of at least one circuit board module while each connector module layer is composed of at least one connector module. Hence, the SoC module structure can be manufactured as a three-dimensional structure, thus allowing highly flexible connections within the SoC module structure.

摘要翻译： 提供了多层片上系统（SoC）模块结构。 多层SoC模块结构包括至少两个电路板模块层和至少一个连接器模块层。 每个连接器模块层夹在两个电路板模块层之间并由此电连接，使得SoC模块结构通过堆叠形成。 每个电路板模块层由至少一个电路板模块组成，而每个连接器模块层由至少一个连接器模块组成。 因此，SoC模块结构可以制造为三维结构，从而允许SoC模块结构内的高度灵活的连接。

公开(公告)号：US07859313B2

公开(公告)日：2010-12-28

申请号：US12489624

申请日：2009-06-23

申请人： Ting Hsu Chien ,  Chi Sheng Lin ,  Chin-Long Wey ,  Chun-Ming Huang ,  Ying-Zong Juang

发明人： Ting Hsu Chien ,  Chi Sheng Lin ,  Chin-Long Wey ,  Chun-Ming Huang ,  Ying-Zong Juang

IPC分类号： H03K5/19 ,  H03K5/22

CPC分类号： H03K5/19 ,  H03K5/1534 ,  H03L7/0891 ,  H03L7/10

摘要： An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2π. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock.

摘要翻译： 边缘丢失检测器结构包括第一检测器，第一延迟单元，第一逻辑门，第二检测器，第二延迟单元和第二逻辑门。 在分别输入到边缘丢失检测器结构中之后，第一和第二检测器检测第一参考信号和第一时钟信号，然后分别由第一和第二逻辑门进行循环抑制，以产生 第二参考信号和呈现小于2＆pgr的相位差的第二时钟信号。 此外，边缘丢失检测器结构产生对应于循环抑制的出现次数的补偿电流。 因此，使用边缘丢失检测器结构的锁相环（PLL）可以避免周期滑移问题并实现锁相的快速采集。

公开(公告)号：US20100277203A1

公开(公告)日：2010-11-04

申请号：US12489624

申请日：2009-06-23

申请人： Ting Hsu Chien ,  Chi Sheng Lin ,  Chin-Long Wey ,  Chun-Ming Huang ,  Ying-Zong Juang

发明人： Ting Hsu Chien ,  Chi Sheng Lin ,  Chin-Long Wey ,  Chun-Ming Huang ,  Ying-Zong Juang

IPC分类号： H03K5/19

CPC分类号： H03K5/19 ,  H03K5/1534 ,  H03L7/0891 ,  H03L7/10

摘要： An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2π. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock.

摘要翻译： 边缘丢失检测器结构包括第一检测器，第一延迟单元，第一逻辑门，第二检测器，第二延迟单元和第二逻辑门。 在分别输入到边缘丢失检测器结构中之后，第一和第二检测器检测第一参考信号和第一时钟信号，然后分别由第一和第二逻辑门进行循环抑制，以产生 第二参考信号和呈现小于2＆pgr的相位差的第二时钟信号。 此外，边缘丢失检测器结构产生对应于循环抑制的出现次数的补偿电流。 因此，使用边缘丢失检测器结构的锁相环（PLL）可以避免周期滑移问题并实现锁相的快速采集。

公开(公告)号：US08274794B2

公开(公告)日：2012-09-25

申请号：US12752345

申请日：2010-04-01

申请人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

发明人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

IPC分类号： H05K7/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K1/14 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K7/00

摘要： A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

摘要翻译： 提供了通过堆叠多个芯片模块形成的三维SoC结构。 三维SoC结构包括至少两个垂直SoC模块和至少一个连接器模块，其中每个连接器模块电连接两个垂直SoC模块。 每个垂直SoC模块通过垂直堆叠至少两个芯片模块构成。 每个芯片模块包括模块电路板和至少一个预设元件。 在每个模块电路板中形成凹部，并设置有用于与相应的至少一个预设元件电连接的第一连接接口。 至少两个垂直SoC模块通过连接器模块连接，形成具有多种功能的三维SoC结构。 此外，形成在模块电路板中的凹部为预设元件提供有效的散热路径。

公开(公告)号：US20100330741A1

公开(公告)日：2010-12-30

申请号：US12570049

申请日：2009-09-30

申请人： Chun-Ming Huang ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chin-Long Wey ,  Chi-Shi Chen ,  Chi-Sheng Lin

发明人： Chun-Ming Huang ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chin-Long Wey ,  Chi-Shi Chen ,  Chi-Sheng Lin

IPC分类号： H01L21/56

CPC分类号： H01L23/3128 ,  H01L23/38 ,  H01L23/467 ,  H01L25/105 ,  H01L25/16 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/19105 ,  H01L2924/00

摘要： A fabrication method for a system-on-chip (SoC) module is provided. The fabrication method includes the steps of providing at least two SoC sub-modules and connecting the SoC sub-modules. The SoC sub-modules are electrically connected with each other by connection interfaces of the SoC sub-modules so as to form the SoC module. As the SoC sub-modules have been verified in advance, the time required for verifying the resulting SoC module can be significantly reduced. As for application-specific SoC modules, they are fabricated by connecting with application-specific SoC sub-modules via the appropriate connection interfaces. Thus, the time and costs for developing SoC modules can both be minimized.

摘要翻译： 提供了一种片上系统（SoC）模块的制造方法。 该制造方法包括提供至少两个SoC子模块并连接SoC子模块的步骤。 SoC子模块通过SoC子模块的连接接口彼此电连接，形成SoC模块。 由于SoC子模块已经被提前验证，所以可以显着地减少验证所得到的SoC模块所需的时间。 对于特定于应用的SoC模块，它们是通过与特定应用的SoC子模块通过适当的连接接口进行连接而制造的。 因此，开发SoC模块的时间和成本都可以最小化。

公开(公告)号：US20100059886A1

公开(公告)日：2010-03-11

申请号：US12292261

申请日：2008-11-14

申请人： Chin-Long Wey ,  Chun-Ming Huang ,  Chien-Ming Wu ,  Chih-Chyan Yang ,  Wei-De Chien

发明人： Chin-Long Wey ,  Chun-Ming Huang ,  Chien-Ming Wu ,  Chih-Chyan Yang ,  Wei-De Chien

IPC分类号： H01L23/48

CPC分类号： H01L25/0655 ,  H01L23/3121 ,  H01L23/538 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/48 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention discloses a carrier structure of a System-on-Chip (SoC) with a custom interface. The carrier structure includes a substrate, at least one common die, at least one custom interface and a molding compound. The common die and the custom interface are disposed on the substrate. The molding compound is used to package the common die which electrically connects to the substrate and the custom interface respectively. The carrier structure which includes the common die can form a complete SoC by connecting to an expansive die through the custom interface. The carrier structure with the common die which can be tested and certified in advance allows reducing and simplifying the developing procedures of the SoC.