公开(公告)号：US06469390B2

公开(公告)日：2002-10-22

申请号：US09296001

申请日：1999-04-21

申请人： Chorng-Ping Chang ,  Kin Ping Cheung ,  Chien-Shing Pai ,  Wei Zhu

发明人： Chorng-Ping Chang ,  Kin Ping Cheung ,  Chien-Shing Pai ,  Wei Zhu

IPC分类号： H01L2348

CPC分类号： H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S977/70 ,  H01L2924/00

摘要： It has been discovered that for semiconductor devices such as MOSFETs, there is significant capacitive coupling in the front-end structure, i.e., the structure from and including the device substrate up to the first metal interconnect level. The invention therefore provides a device comprising a silicon substrate, an isolation structure in the substrate (e.g., shallow trench isolation), an active device structure (e.g., a transistor structure), a dielectric layer over the active device structure, and a metal interconnect layer over the dielectric layer (metal-1 level). At least one of the dielectric components of the front-end structure comprise a material exhibiting a dielectric constant less than 3.5. This relatively low dielectric constant material reduces capacitive coupling in the front-end structure, thereby providing improved properties in the device.

摘要翻译： 已经发现，对于诸如MOSFET的半导体器件，在前端结构中存在显着的电容耦合，即从器件衬底到第一金属互连级别的结构。 因此，本发明提供了一种包括硅衬底，衬底中的隔离结构（例如，浅沟槽隔离），有源器件结构（例如，晶体管结构），有源器件结构上的介电层以及金属互连 层（介电层）（金属-1层）。 前端结构的介电部件中的至少一个包括介电常数小于3.5的材料。 这种相对低的介电常数材料减少了前端结构中的电容耦合，从而在器件中提供了改进的特性。

公开(公告)号：US06566224B1

公开(公告)日：2003-05-20

申请号：US08903974

申请日：1997-07-31

申请人： Chorng-Ping Chang ,  Chien-Shing Pai

发明人： Chorng-Ping Chang ,  Chien-Shing Pai

IPC分类号： H01L2176

CPC分类号： H01L21/76235

摘要： The invention is a process for device fabrication that utilizes shallow trench isolation. The process involves the steps of forming an oxidation barrier region, e.g., silicon nitride, above a silicon substrate, providing an opening in the oxidation barrier region and in any underlying regions deposited on the silicon, providing a trench in the silicon substrate at the opening, depositing a dielectric material such as silicon dioxide in the trench, typically planarizing the trench silicon dioxide, and subsequently performing an oxidation step. The oxidation step rounds the otherwise sharp corners of the silicon at the area where the trench silicon dioxide meets the pad oxide. The invention thereby reduces or eliminates sharp corners that contribute to leakage current.

摘要翻译： 本发明是利用浅沟槽隔离的器件制造工艺。 该方法包括以下步骤：在硅衬底之上形成氧化阻挡区域，例如氮化硅，在氧化阻挡区域和沉积在硅上的任何下层区域提供开口，在开口处的硅衬底中提供沟槽 ，在沟槽中沉积诸如二氧化硅的电介质材料，通常对沟槽二氧化硅进行平面化，随后执行氧化步骤。 在沟槽二氧化硅与衬垫氧化物相遇的区域，氧化步骤回绕硅的其它尖角。 因此，本发明减少或消除了有助于泄漏电流的尖角。

公开(公告)号：US06312766B1

公开(公告)日：2001-11-06

申请号：US09205840

申请日：1998-12-04

申请人： Chien-Shing Pai ,  Wei Zhu

发明人： Chien-Shing Pai ,  Wei Zhu

IPC分类号： C23C1448

CPC分类号： H01L21/0212 ,  C23C14/06 ,  C23C14/0605 ,  H01L21/02271 ,  H01L21/312 ,  H01L21/76813

摘要： Ion beam deposition, using a carbon- and fluorine-containing source or sources, is used to form a fluorinated diamond-like carbon layer in a device, the FDLC layer exhibiting a dielectric constant of 3.0 or less along with a thermal stability of at least 400° C. During the ion beam deposition, due to the unique nature of carbon chemistry, the carbon atoms combine at the substrate surface to form all possible combinations of sp1, sp2 and sp3 bonds. However, ion beam etching occurs along with deposition, such that atoms of the weaker carbon structures—carbyne and graphite—are removed preferentially. This leads to a buildup of a diamond-like, sp3-bonded structure with fluorine atoms, it is believed, substituted for some carbon atoms within the structure, this structure providing the desirable properties of the layer.

摘要翻译： 使用含碳和氟的源或离子源的离子束沉积在器件中形成氟化类金刚石碳层，FDLC层的介电常数为3.0以下，热稳定性至少为 在离子束沉积期间，由于碳化学的独特性质，碳原子在衬底表面结合形成sp1，sp2和sp3键的所有可能的组合。 然而，离子束蚀刻与沉积一起发生，使得较弱的碳结构的原子 - 碳晶体和石墨 - 被优先除去。 这导致了具有氟原子的类金刚石，sp3键合结构的结构，据信这被取代了结构内的一些碳原子，该结构提供了该层所需的性质。

公开(公告)号：US06147407A

公开(公告)日：2000-11-14

申请号：US49256

申请日：1998-03-27

申请人： Sungho Jin ,  Ruichen Liu ,  Chien-Shing Pai ,  Wei Zhu

发明人： Sungho Jin ,  Ruichen Liu ,  Chien-Shing Pai ,  Wei Zhu

IPC分类号： C23C14/06 ,  C23C14/22 ,  C23C14/34 ,  H01L21/312 ,  H01L23/532 ,  H01L23/48

CPC分类号： C23C14/225 ,  C23C14/0605 ,  C23C14/3464 ,  H01L21/3127 ,  H01L23/5329 ,  H01L2924/0002

摘要： The invention provides a device containing a low .kappa., hydrogen-free a-C:F layer with good adhesion and thermal stability. It was found that the combination of desirable properties was attainable by a relatively easy process, as compared to processes that utilize gaseous sources, such as CVD. Specifically, the a-C:F layer is formed by sputter deposition, using only solid sources for the fluorine and carbon, and in the absence of any intentionally-added hydrogen-containing source. The sputtering is performed such that the layer contains 20 to 60 at. % fluorine, and also, advantageously, such that the a-C:F exhibits a bandgap of about 2.0 eV or greater. The a-C:F layer formed by the process of the invention exhibits a dielectric constant, at 1 MHz and room temperature, of 3.0 or less, advantageously 2.5 or less, and more advantageously 2.1 or less, along with being thermally stable up to at least 350.degree. C., advantageously 450.degree. C., and exhibiting a stress of about 100 MPa or less, in absolute value.

摘要翻译： 本发明提供含有低κ，无氢a-C：F层的装置，其具有良好的粘附性和热稳定性。 已经发现，与使用气体源（例如CVD）的方法相比，期望性质的组合可通过相对容易的方法获得。 具体地，通过溅射沉积形成a-C：F层，仅使用固体源作为氟和碳，并且在没有任何有意添加的含氢源的情况下。 进行溅射使得该层含有20至60at。 ％氟，并且还有利地使得a-C：F表现出约2.0eV或更大的带隙。 通过本发明的方法形成的aC：F层在1MHz和室温下表现出3.0或更小，有利地为2.5或更小，更优选为2.1或更小的介电常数，并且至少热稳定 350℃，有利地450℃，绝对值为约100MPa以下。

公开(公告)号：US6149778A

公开(公告)日：2000-11-21

申请号：US196486

申请日：1998-11-19

申请人： Sungho Jin ,  Ruichen Liu ,  Chien-Shing Pai ,  Wei Zhu

发明人： Sungho Jin ,  Ruichen Liu ,  Chien-Shing Pai ,  Wei Zhu

IPC分类号： H01L23/532 ,  C23C14/34

CPC分类号： H01L23/5329 ,  H01L2924/0002

摘要： The invention provides a device containing a low .kappa., hydrogen-free a-C:F layer with good adhesion and thermal stability. It was found that the combination of desirable properties was attainable by a relatively easy process, as compared to processes that utilize gaseous sources, such as CVD. Specifically, the a-C:F layer is formed by sputter deposition, using only solid sources for the fluorine and carbon, and in the absence of any intentionally-added hydrogen-containing source. The sputtering is performed such that the layer contains 20 to 60 at. % fluorine, and also, advantageously, such that the a-C:F exhibits a bandgap of about 2.0 eV or greater. The a-C:F layer formed by the process of the invention exhibits a dielectric constant, at 1 MHz and room temperature, of 3.0 or less, advantageously 2.5 or less, along with being thermally stable up to at least 350.degree. C., advantageously 450.degree. C., and exhibiting a stress of about 100 MPa or less, in absolute value.

摘要翻译： 本发明提供含有低κ，无氢a-C：F层的装置，其具有良好的粘附性和热稳定性。 已经发现，与使用气体源（例如CVD）的方法相比，期望性质的组合可通过相对容易的方法获得。 具体地，通过溅射沉积形成a-C：F层，仅使用固体源作为氟和碳，并且在没有任何有意添加的含氢源的情况下。 进行溅射使得该层含有20至60at。 ％氟，并且还有利地使得a-C：F表现出约2.0eV或更大的带隙。 通过本发明的方法形成的aC：F层在1MHz和室温下表现出3.0或更小，有利地为2.5或更小的介电常数，并且热稳定性高达至少350℃，有利地为450 并且以绝对值表现出约100MPa以下的应力。

公开(公告)号：US20050189488A1

公开(公告)日：2005-09-01

申请号：US10789091

申请日：2004-02-27

申请人： Chien-Shing Pai ,  Stanley Pau ,  Joseph Taylor

发明人： Chien-Shing Pai ,  Stanley Pau ,  Joseph Taylor

IPC分类号： G01N27/62 ,  B01D59/44 ,  H01J49/00 ,  H01J49/26 ,  H01J49/28 ,  H01J49/42

CPC分类号： H01J49/0018 ,  H01J49/424

摘要： An apparatus includes a semiconductor or dielectric wafer-substrate and first and second multi-layer structures located over the wafer-substrate. The first multi-layer structure includes an ionizer or an electronic ion detector. The second multi-layer structure includes an ion trap having entrance and exit ports. The ionizer or electronic ion detector has a port coupled to one of the ports of the ion trap.

公开(公告)号：US06852648B2

公开(公告)日：2005-02-08

申请号：US10435561

申请日：2003-05-09

申请人： Omkaram Nalamasu ,  Chien-Shing Pai ,  Elsa Reichmanis ,  Shu Yang

发明人： Omkaram Nalamasu ,  Chien-Shing Pai ,  Elsa Reichmanis ,  Shu Yang

IPC分类号： C08G77/442 ,  C08L71/02 ,  C09D183/04 ,  H01L21/312 ,  H01L21/768 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02126 ,  C08G77/442 ,  C08G2650/58 ,  C08L71/02 ,  C09D183/04 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/312 ,  H01L21/7682 ,  Y10S438/96 ,  C08L83/00

摘要： A process for fabricating an integrated semiconductor device with a low dielectric constant material and an integrated semiconductor device with the low dielectric constant material interposed between two conductors is disclosed. The low dielectric constant material has a dielectric constant of less than about 2.8. The low dielectric constant material is a porous glass material with an average pore size of less than about 10 nm. The low dielectric constant material is formed on a semiconductor substrate with circuit lines thereover by combining an uncured and unmodified glass resin with an amphiphilic block copolymer. The amphiphilic block copolymer is miscible in the uncured glass resin. The mixture is applied onto the semiconductor substrate and the glass resin is cured. The glass resin is further processed to decompose or otherwise remove residual block copolymer from the cured glass resin.

摘要翻译： 公开了一种制造具有低介电常数材料的集成半导体器件和介于两个导体之间的低介电常数材料的集成半导体器件的工艺。 低介电常数材料的介电常数小于约2.8。 低介电常数材料是平均孔径小于约10nm的多孔玻璃材料。 低介电常数材料通过将未固化和未改性的玻璃树脂与两亲性嵌段共聚物组合而形成在具有电路线的半导体衬底上。 两亲嵌段共聚物可与未固化的玻璃树脂混溶。 将混合物施加到半导体衬底上并使玻璃树脂固化。 进一步处理玻璃树脂以从固化的玻璃树脂中分解或以其它方式除去残留的嵌段共聚物。

公开(公告)号：US07452741B2

公开(公告)日：2008-11-18

申请号：US11425100

申请日：2006-06-19

申请人： Vladimir A. Aksyuk ,  Nagesh R. Basavanhally ,  Omar D. Lopez ,  Chien-Shing Pai

发明人： Vladimir A. Aksyuk ,  Nagesh R. Basavanhally ,  Omar D. Lopez ,  Chien-Shing Pai

IPC分类号： H01L21/00

CPC分类号： B81C1/00476 ,  B81B2201/038 ,  B81C1/00801

摘要： The present invention provides a process for manufacturing an apparatus. The process, in one embodiment, includes providing a micro-electro-mechanical system (MEMS) device, the micro-electro-mechanical system (MEMS) device including an actuator coupled to a movable feature, sacrificial material fixing the actuator and movable feature with respect to one another, and a layer of material located over the actuator, movable feature and sacrificial material. The process may further include removing only a portion of the layer of material to expose the sacrificial material, and subjecting the exposed sacrificial material to an etchant to release the movable feature.

摘要翻译： 本发明提供一种制造装置的方法。 在一个实施例中，该过程包括提供微机电系统（MEMS）装置，微机电系统（MEMS）装置包括耦合到可移动特征的致动器，将致动器和可移动特征固定的牺牲材料 相对于彼此，以及位于致动器上方的材料层，可移动特征和牺牲材料。 该方法还可以包括仅去除材料层的一部分以暴露牺牲材料，以及将暴露的牺牲材料经历蚀刻剂以释放可移动特征。

公开(公告)号：US5616518A

公开(公告)日：1997-04-01

申请号：US333900

申请日：1994-11-03

申请人： Pang-Dow Foo ,  Chien-Shing Pai

发明人： Pang-Dow Foo ,  Chien-Shing Pai

IPC分类号： H01L21/285 ,  C23C16/32 ,  C23C16/50 ,  C23C16/511 ,  H01L21/28 ,  H01L21/768 ,  H01L21/441

CPC分类号： H01L21/76843

摘要： Integrated circuits employing titanium nitride are significantly improved by using a specific method for formation of the titanium nitride in the device fabrication. In particular, a plasma such as one formed in an electron cyclotron resonance apparatus is employed to dissociate a source of nitrogen and a source of hydrogen and the dissociation products are combined at the integrated circuit deposition substrate with titanium tetrachloride. The resulting deposition is essentially devoid of chlorine and has advantageous step-coverage properties.

摘要翻译： 使用氮化钛的集成电路通过在器件制造中使用用于形成氮化钛的具体方法而显着改善。 特别地，使用诸如在电子回旋共振装置中形成的等离子体来解离氮源和氢源，并且解离产物在集成电路沉积衬底与四氯化钛组合。 所得到的沉积物基本上不含氯，并且具有有利的步骤覆盖性能。

公开(公告)号：US07081623B2

公开(公告)日：2006-07-25

申请号：US10656432

申请日：2003-09-05

申请人： Chien-Shing Pai ,  Stanley Pau

发明人： Chien-Shing Pai ,  Stanley Pau

IPC分类号： C23F1/00

CPC分类号： H01J49/424 ,  B81B1/00 ,  H01J49/0018

摘要： An apparatus for an ion trap includes a semiconductor or dielectric wafer with front and back surfaces, a sequence of alternating conductive and dielectric layers formed over said front surface, and a bottom conductive layer. The sequence includes top and middle conductive layers, wherein the middle conductive layer is closer to the wafer than the top conductive layer. The middle conductive layer includes a substantially right cylindrical cavity that crosses a width of the middle conductive layer. The top and bottom conductive layers cap respective first and second ends of the cavity. The top conductive layer includes a hole that forms a first access port to the cavity. The wafer includes via through the width of the wafer. The via provides another access to the cavity via the back surface of the wafer. The wafer is substantially thicker than the sequence of layers.

摘要翻译： 用于离子阱的装置包括具有前表面和后表面的半导体或介电晶片，在所述前表面上形成交替的导电和电介质层的序列，以及底部导电层。 该序列包括顶部和中间导电层，其中中间导电层比顶部导电层更靠近晶片。 中间导电层包括穿过中间导电层的宽度的基本上圆柱形的空腔。 顶部和底部导电层分别覆盖空腔的第一和第二端。 顶部导电层包括形成到空腔的第一进入端口的孔。 晶片包括穿过晶片宽度的通孔。 通孔经由晶片的后表面提供对腔的另一访问。 晶片基本上比层序列厚。