公开(公告)号：US20080224326A1

公开(公告)日：2008-09-18

申请号：US12127794

申请日：2008-05-27

申请人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

发明人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad. The bump is disposed on the bump pad.

摘要翻译： 一种芯片结构，包括半导体衬底，多个电介质层，多个电路层，钝化层，金属层和至少一个凸块。 半导体衬底具有位于半导体衬底的表面层上的多个电子器件。 电介质层依次层叠在半导体基板上，具有多个通路孔。 电路层设置在电介质层之一上，其中电路层通过通孔彼此电连接并电连接到电子器件。 钝化层设置在电路层和电介质层之上，其中钝化层包括暴露金属层之一的开口。 金属层设置在钝化层上，其中金属层至少包括凸块焊盘和至少一个测试焊盘，该焊盘与测试焊盘电连接。 凸块设置在凸块上。

公开(公告)号：US20110049515A1

公开(公告)日：2011-03-03

申请号：US12941069

申请日：2010-11-07

申请人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

发明人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

IPC分类号： H01L23/492 ,  H01L23/482

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.

摘要翻译： 一种芯片结构，包括硅衬底，MOS器件，电介质层，金属化结构，钝化层，多个金属层和聚合物层。 金属化结构包括在第一电路层上的第一电路层和第二电路层，并且包括镶嵌电镀铜。 钝化层在金属化结构和电介质层之上，钝化层包括暴露金属化结构的接触点的第一开口。 聚合物层设置在钝化层和第一金属层之上，聚合物层中的第二开口在第一金属层的第二接触点之上，聚合物层覆盖第一金属层的顶表面和侧壁。 第二接触点通过第一开口连接到第一接触点，第二开口不垂直于第一开口。

公开(公告)号：US07855461B2

公开(公告)日：2010-12-21

申请号：US12127794

申请日：2008-05-27

申请人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

发明人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

IPC分类号： H01L23/43

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad. The bump is disposed on the bump pad.

摘要翻译： 一种芯片结构，包括半导体衬底，多个电介质层，多个电路层，钝化层，金属层和至少一个凸块。 半导体衬底具有位于半导体衬底的表面层上的多个电子器件。 电介质层依次层叠在半导体基板上，具有多个通路孔。 电路层设置在电介质层之一上，其中电路层通过通孔彼此电连接并电连接到电子器件。 钝化层设置在电路层和电介质层之上，其中钝化层包括暴露金属层之一的开口。 金属层设置在钝化层上，其中金属层至少包括凸块焊盘和至少一个测试焊盘，该焊盘与测试焊盘电连接。 凸块设置在凸块上。

公开(公告)号：US08674507B2

公开(公告)日：2014-03-18

申请号：US10855086

申请日：2004-05-27

申请人： Chien-Kang Chou ,  Chiu-Ming Chou ,  Li-Ren Lin ,  Chu-Fu Lin

发明人： Chien-Kang Chou ,  Chiu-Ming Chou ,  Li-Ren Lin ,  Chu-Fu Lin

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0231 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/731 ,  H01L2224/73207 ,  H01L2224/81411 ,  H01L2224/85444 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/01016 ,  H01L2224/13099 ,  H01L2224/45099

摘要： A chip structure comprising a substrate, a plurality of wire bonding pads and a plurality of solder pads is provided. Gold bumps or gold pads can be formed on the wire bonding pads while solder bumps can be formed on the solder pads concurrently. Alternatively, both wire bonding pads and solder pads can be formed of the same metal stack.

摘要翻译： 提供了包括基板，多个引线接合焊盘和多个焊盘的芯片结构。 可以在引线接合焊盘上形成金焊盘或金焊盘，同时可以在焊盘上形成焊料凸块。 或者，两个引线接合焊盘和焊盘可以由相同的金属堆叠形成。

公开(公告)号：US20080083298A1

公开(公告)日：2008-04-10

申请号：US11544571

申请日：2006-10-10

申请人： Chu-Fu Lin

发明人： Chu-Fu Lin

IPC分类号： F16C15/00

CPC分类号： F16C15/00 ,  F16C2361/55 ,  F16F15/30 ,  Y10T74/2121

摘要： A counter weight flywheel includes an inner cylindrical body and an outer cylindrical body disposed between an upper faceplate and a lower faceplate. A shaft tube is positioned in the inner cylindrical body, and plural tensile bars are inserted in the inner cylindrical body, respectively having one end secured on the fixing members of the shaft tube and the other end fixed on the inner wall of the outer cylindrical body. Plural reinforcing bars and plural reserve tubes are respectively fixed between the inner and the outer cylindrical body. A counter weight area formed between the inner and the outer cylindrical body is filled up with concrete or iron sand, and the inner cylindrical body has its interior forming a hollow area. Thus, the counter weight flywheel is made by combining iron plates and concrete or iron sand.

摘要翻译： 配重飞轮包括内圆筒体和设置在上面板和下面板之间的外筒体。 轴筒位于内筒体内，多个拉伸杆插入内筒体内，其一端固定在轴管的固定部件上，另一端固定在外筒体的内壁上 。 多个钢筋和多个储备管分别固定在内筒体和外筒体之间。 在内筒体和外筒体之间形成的配重区域填充有混凝土或铁砂，内筒体的内部形成中空区域。 因此，配重飞轮是通过铁板和混凝土或铁砂组合制成的。

公开(公告)号：US20060237969A1

公开(公告)日：2006-10-26

申请号：US11277700

申请日：2006-03-28

申请人： Chu-Fu Lin

发明人： Chu-Fu Lin

IPC分类号： H02K7/18 ,  F03G7/08 ,  F02B63/04

CPC分类号： H02K53/00

摘要： An energy-saving environmentally friendly generating system includes at least one starting system, a generating system, a transmission gear system, and at least one weighting system. Speed ratios of the transmission gear system are utilized, and an external power is used to start the starting system. The speed changes of large and small gears create torques for releasing energy that is multiple times of the primitive energy of the starting system. The weighting system rotates and creates a gravitational force to release multifold energy for counterbalancing the load of generating and the load of electricity consumption of the generating system. The generating system can thus be started. When the generating system reaches its rated generating speed, a portion of electricity is directly transmitted to the starting system, thereby achieving continuous operation for generating electricity.

摘要翻译： 节能环保发电系统包括至少一个启动系统，发电系统，变速器齿轮系统和至少一个加权系统。 利用传动齿轮系统的转速比，并且使用外部动力来启动起动系统。 大齿轮和小齿轮的转速产生扭矩，释放能量，这是启动系统的原始能量的多倍。 加权系统旋转并产生重力以释放多重能量以平衡发电负载和发电系统的用电负荷。 因此可以启动发电系统。 当发电系统达到其额定发电速度时，一部分电力直接发送到起动系统，从而实现连续的发电运行。

公开(公告)号：US20050121804A1

公开(公告)日：2005-06-09

申请号：US10730834

申请日：2003-12-08

申请人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

发明人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

IPC分类号： H01L23/31 ,  H01L23/48 ,  H01L23/485

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor substrate has a plurality of electronic devices positioned on a surface layer of the semiconductor substrate. The dielectric layers are sequentially stacked on the semiconductor substrate and have a plurality of via holes. The circuit layers are disposed on one of the dielectric layers, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. The passivation layer is disposed over the circuit layers and the dielectric layers, wherein the passivation layer comprises an opening that exposes one of the metal layers. The metal layer is disposed over the passivation layer, wherein the metal layer comprises at least a bump pad and at least a testing pad, the bump pad electrically connecting with the testing pad. The bump is disposed on the bump pad.

摘要翻译： 一种芯片结构，包括半导体衬底，多个电介质层，多个电路层，钝化层，金属层和至少一个凸块。 半导体衬底具有位于半导体衬底的表面层上的多个电子器件。 电介质层依次层叠在半导体基板上，具有多个通路孔。 电路层设置在电介质层之一上，其中电路层通过通孔彼此电连接并电连接到电子器件。 钝化层设置在电路层和电介质层之上，其中钝化层包括暴露金属层之一的开口。 金属层设置在钝化层上，其中金属层至少包括凸块焊盘和至少一个测试焊盘，该焊盘与测试焊盘电连接。 凸块设置在凸块上。

公开(公告)号：US20050017355A1

公开(公告)日：2005-01-27

申请号：US10855086

申请日：2004-05-27

申请人： Chien-Kang Chou ,  Chiu-Ming Chou ,  Li-Ren Lin ,  Chu-Fu Lin

发明人： Chien-Kang Chou ,  Chiu-Ming Chou ,  Li-Ren Lin ,  Chu-Fu Lin

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L25/065 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0231 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/731 ,  H01L2224/73207 ,  H01L2224/81411 ,  H01L2224/85444 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/01016 ,  H01L2224/13099 ,  H01L2224/45099

摘要： A chip structure comprising a substrate, a plurality of wire bonding pads and a plurality of solder pads is provided. Gold bumps or gold pads can be formed on the wire bonding pads while solder bumps can be formed on the solder pads concurrently. Alternatively, both wire bonding pads and solder pads can be formed of the same metal stack.

摘要翻译： 提供了包括基板，多个引线接合焊盘和多个焊盘的芯片结构。 可以在引线接合焊盘上形成金焊盘或金焊盘，同时可以在焊盘上形成焊料凸块。 或者，两个引线接合焊盘和焊盘可以由相同的金属堆叠形成。

公开(公告)号：US07977803B2

公开(公告)日：2011-07-12

申请号：US12941069

申请日：2010-11-07

申请人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

发明人： Nick Kuo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Chu-Fu Lin

IPC分类号： H01L23/43

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48647 ,  H01L2224/73207 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.

摘要翻译： 一种芯片结构，包括硅衬底，MOS器件，电介质层，金属化结构，钝化层，多个金属层和聚合物层。 金属化结构包括在第一电路层上的第一电路层和第二电路层，并且包括镶嵌电镀铜。 钝化层在金属化结构和电介质层之上，钝化层包括暴露金属化结构的接触点的第一开口。 聚合物层设置在钝化层和第一金属层之上，聚合物层中的第二开口在第一金属层的第二接触点之上，聚合物层覆盖第一金属层的顶表面和侧壁。 第二接触点通过第一开口连接到第一接触点，第二开口不垂直于第一开口。

公开(公告)号：US20090137097A1

公开(公告)日：2009-05-28

申请号：US11945115

申请日：2007-11-26

申请人： Chu-Fu Lin ,  Kai-Kuang Ho ,  Kuo-Ming Chen

发明人： Chu-Fu Lin ,  Kai-Kuang Ho ,  Kuo-Ming Chen

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2924/19041

摘要： A method for dicing a wafer including the following steps is provided. First, a carrier tape is attached to a first side of the wafer. Then, a patterned photoresist layer exposing a scribe line region of the wafer is formed on a second side of the wafer, in which the second side is the opposite side of the first side. After that, a cutting process is performed to the scribe line region from the second side of the wafer to the first side of the wafer through non-mechanical force.

摘要翻译： 提供了一种用于切割晶片的方法，包括以下步骤。 首先，将载带附接到晶片的第一侧。 然后，在晶片的第二侧上形成暴露晶片的划线区域的图案化光致抗蚀剂层，其中第二侧是第一侧的相对侧。 之后，通过非机械力对从晶片的第二侧到晶片的第一侧的划线区域进行切割处理。