公开(公告)号：US10014183B2

公开(公告)日：2018-07-03

申请号：US15523742

申请日：2015-11-09

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

发明人： Shay Reboh ,  Laurent Grenouillet ,  Yves Morand

IPC分类号： H01L21/308 ,  H01L21/311 ,  H01L27/12

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/1203

摘要： A method for producing at least one pattern in a layer resting on a substrate, including: a) making amorphous at least one first block of an upper layer of crystalline material resting on a first amorphous supporting layer, while the crystalline structure of a second block of the upper layer that adjoins and is juxtaposed with the first block is preserved; b) partially recrystallizing the first block by using at least one side surface of the second block that is in contact with the first block as an area for the start of a recrystallization front, the partial recrystallization being carried out to preserve a region of amorphous material in the first block; c) selectively etching the amorphous material of the upper layer with respect to the crystalline material of the upper layer to form at least one first pattern in the upper layer.

公开(公告)号：US09911820B2

公开(公告)日：2018-03-06

申请号：US15464763

申请日：2017-03-21

申请人： Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

发明人： Cyrille Le Royer ,  Frederic Boeuf ,  Laurent Grenouillet ,  Louis Hutin ,  Yves Morand

IPC分类号： H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

CPC分类号： H01L29/4983 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66628

摘要： A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

公开(公告)号：US09831319B2

公开(公告)日：2017-11-28

申请号：US15058615

申请日：2016-03-02

申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives

发明人： Julien Borrel ,  Louis Hutin ,  Yves Morand ,  Fabrice Nemouchi ,  Heimanu Niebojewski

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L23/535 ,  H01L29/423 ,  H01L29/51 ,  H01L29/772

CPC分类号： H01L29/66553 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0895 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/772

摘要： A field-effect transistor, including a source, drain and channel formed in a semiconductor layer a gate stack placed above the channel, including a metal electrode, a first layer of electrical insulator placed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; a metal contact placed plumb with the source or drain and at least partially plumb with said gate stack; and a third layer of electrical insulator placed between said metal contact and said source or said drain.

公开(公告)号：US09536951B2

公开(公告)日：2017-01-03

申请号：US14849060

申请日：2015-09-09

申请人： Commissariat a l'Energie Atomique et aux Energies Alternatives

发明人： Sylvain Maitrejean ,  Emmanuel Augendre ,  Louis Hutin ,  Yves Morand

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/1054 ,  H01L29/66795 ,  H01L29/7853

摘要： FinFET transistor comprising at least: one fin that forms a channel, a source and a drain, comprising an alternating stack of first portions of silicon-rich SiGe and of second portions of a dielectric or semiconductor material, and third portions of germanium-rich SiGe arranged at least against lateral faces of the first portions, one gate that covers the channel, and wherein each one of the third portions comprises faces with a crystal orientation [111] covered by the gate.

摘要翻译： FinFET晶体管至少包括：形成沟道的一个鳍，源极和漏极，包括富硅SiGe的第一部分和电介质或半导体材料的第二部分的交替堆叠，以及富含锗的SiGe的第三部分 至少布置在所述第一部分的侧面上，一个栅极覆盖所述通道，并且其中所述第三部分中的每一个包括被所述栅极覆盖的晶体取向[111]的面。

公开(公告)号：US20150091089A1

公开(公告)日：2015-04-02

申请号：US14499545

申请日：2014-09-29

申请人： STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

发明人： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer ,  Olivier Rozeau

IPC分类号： H01L29/51 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/515 ,  H01L29/0843 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/78

摘要： A MOS transistor has a gate insulator layer that is made of a material of high dielectric constant deposited on a substrate. The gate insulator layer extends, with a constant thickness, under and beyond a gate stack. Spacers of low dielectric constant are formed on either side of the gate stack and vertically separated from the substrate by the extension of the gate insulator layer beyond the sides of the gate stack. The spacers of low dielectric constant are preferably air spacers.

摘要翻译： MOS晶体管具有由沉积在衬底上的高介电常数材料制成的栅极绝缘体层。 栅极绝缘体层以恒定的厚度延伸到栅极堆叠之下和之外。 通过栅极绝缘体层的延伸超过栅极叠层的侧面，在栅极叠层的任一侧上形成具有低介电常数的隔板并与衬底垂直分离。 低介电常数的间隔物优选为空气间隔物。

公开(公告)号：US09935019B2

公开(公告)日：2018-04-03

申请号：US15261226

申请日：2016-09-09

申请人： Commissariat a l'Energie Atomique et aux Energies Alternatives

发明人： Shay Reboh ,  Laurent Grenouillet ,  Frederic Milesi ,  Yves Morand ,  Francois Rieutord

IPC分类号： H01L21/84 ,  H01L21/265 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/266 ,  H01L21/02 ,  H01L21/223 ,  H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7846

摘要： Method for creation of stressed channel structure transistors wherein at least one amorphizing ion implantation of the surface layer of a substrate of the semiconductor-on-insulator type is carried out through openings in a mask, so as to render zones of the surface layers amorphous and to induce relaxation of a zone intended to form a channel and located between the zones that have been rendered amorphous, the relaxation being carried out in a direction orthogonal to that in which it is intended that the channel current flows.

公开(公告)号：US09911827B2

公开(公告)日：2018-03-06

申请号：US15372930

申请日：2016-12-08

申请人： Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

发明人： Louis Hutin ,  Julien Borrel ,  Yves Morand ,  Fabrice Nemouchi

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC分类号： H01L29/66643 ,  H01L29/0895 ,  H01L29/66636 ,  H01L29/7839

摘要： A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer.

公开(公告)号：US20170271470A1

公开(公告)日：2017-09-21

申请号：US15464763

申请日：2017-03-21

申请人： Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

发明人： Cyrille LE ROYER ,  Frederic Boeuf ,  Laurent Grenouillet ,  Louis Hutin ,  Yves Morand

IPC分类号： H01L29/49 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L23/535

CPC分类号： H01L29/4983 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66628

摘要： A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

公开(公告)号：US09502558B2

公开(公告)日：2016-11-22

申请号：US14791713

申请日：2015-07-06

申请人： Commissariat a L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS (CROLLES 2) SAS

发明人： Shay Reboh ,  Laurent Grenouillet ,  Cyrille Le Royer ,  Sylvain Maitrejean ,  Yves Morand

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L29/66

CPC分类号： H01L29/7847 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26506 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/7849

摘要： Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorization technique in which regions located under the insulation layer of the substrate (FIG. 6) are amorphized, before the transistor gate is made.

摘要翻译： 使用在晶体管栅极制造之前利用其中位于衬底（图6）的绝缘层下方的区域非晶化的SMT应力存储技术的半导体绝缘体型晶体管的晶体管的沟道区域的方法 。

公开(公告)号：US09269570B2

公开(公告)日：2016-02-23

申请号：US13860845

申请日：2013-04-11

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS (CROLLES 2) SAS

发明人： Yves Morand ,  Charles Baudot ,  Fabrice Nemouchi

IPC分类号： H01L21/02 ,  H01L21/285

CPC分类号： H01L21/02381 ,  H01L21/28518

摘要： A method is provided for producing a microelectronic device with plural zones made of a metal and semiconductor compound, from semiconductor zones made of different semiconductor materials, and on which a thin semiconductor layer is formed prior to the deposition of a metal layer so as to lower the nucleation barrier of the semiconductor zones when reacting with the metal layer.

摘要翻译： 提供了一种从由不同半导体材料制成的半导体区域制造具有由金属和半导体化合物制成的多个区域的微电子器件的方法，并且在沉积金属层之前在其上形成薄的半导体层以便降低 当与金属层反应时，半导体区的成核势垒。