公开(公告)号：US20160172027A1

公开(公告)日：2016-06-16

申请号：US14571949

申请日：2014-12-16

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Ehsan Tahmasebian ,  Hyoung Seub Rhie ,  Peter Gillingham

IPC: G11C13/00 ,  H01L51/00 ,  H01L51/10

CPC classification number: G11C13/0016 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C2013/0054 ,  G11C2213/34 ,  G11C2213/56 ,  G11C2213/72 ,  G11C2213/73 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L51/0595

Abstract: A integrated circuit device with a polymer memory array includes active circuits formed in lower layers of a multi-level interconnect structure and a semiconductor substrate and also includes an array of polymer memory cells formed in an upper interconnect level having a plurality of cell node electrodes and source line electrodes for the polymer memory array, each polymer memory cell including a passive layer having at least one conductivity-facilitating compound that is formed on top and sidewall surfaces of a source line electrode, and an active layer having an impedance state that can change that is formed on top and sidewall surfaces of an adjacent cell node electrode with sufficient thickness to make direct physical contact with the passive layer.

Abstract translation: 具有聚合物存储器阵列的集成电路器件包括形成在多层互连结构的下层中的有源电路和半导体衬底，并且还包括形成在具有多个单元节点电极的上部互连电平中的聚合物存储器单元的阵列， 用于聚合物存储器阵列的源极线电极，每个聚合物存储单元包括具有形成在源极线电极的顶壁和侧壁表面上的至少一种导电性促进化合物的钝化层，以及具有可改变的阻抗状态的有源层 其形成在相邻电池节点电极的顶壁和侧壁表面上，具有足够的厚度以与被动层直接物理接触。

公开(公告)号：US09236095B2

公开(公告)日：2016-01-12

申请号：US14148336

申请日：2014-01-06

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Peter Gillingham

IPC: G11C11/34 ,  G11C5/14 ,  G11C16/10 ,  G11C16/12 ,  G11C16/30 ,  H01L25/065 ,  H01L23/00

CPC classification number: G11C5/147 ,  G11C5/145 ,  G11C16/10 ,  G11C16/12 ,  G11C16/30 ,  H01L24/04 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13009 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1434 ,  Y10T29/49117 ,  H01L2924/00

Abstract: A method, system and apparatus for sharing internal power supplies in integrated circuit devices is described. A multiple device integrated circuit 200 including multiple integrated circuits 202-205 each having internal power supplies is contained in an enclosure 201. Integrated circuits 202-205 are described showing how to make external connection to internal power supplies. Connections 208-212 are provided to the internal power supplies of each of devices 202-205. Another embodiment 500 of the system provides for disablement of regulators in multiple integrated circuits 502, 503, and 504 by another integrated circuit 501 for power consumption reduction. The method FIG. 6 includes providing devices and connecting the internal power supplies together. An integrated circuit 501 with a power supply 400 adapted to the system and method with additional circuitry 308, 404 and 402 for disabling a regulator 306 is described.

Abstract translation: 描述了用于在集成电路设备中共享内部电源的方法，系统和装置。 包含多个具有内部电源的集成电路202-205的多器件集成电路200包含在外壳201中。描述了如何进行与内部电源的外部连接的集成电路202-205。 连接208-212被提供给每个设备202-205的内部电源。 该系统的另一个实施例500提供了另一个集成电路501对多个集成电路502,503和504中的稳压器的禁用，以降低功耗。 方法 6包括提供设备并将内部电源连接在一起。 描述了具有适用于具有用于禁用调节器306的附加电路308,404和402的系统和方法的电源400的集成电路501。

公开(公告)号：US09177863B2

公开(公告)日：2015-11-03

申请号：US13951132

申请日：2013-07-25

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Peter Gillingham

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/82 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L21/82 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Abstract translation: 半导体器件具有安装在基板上的多个堆叠的半导体管芯。 每个模具具有相似的尺寸。 每个管芯具有沿着管芯的接合边缘布置的第一多个接合焊盘。 将第一组骰子安装到衬底上，其中接合边缘沿第一方向定向。 将第二组骰子安装到基板上，其中接合边缘沿与第一方向相反的第二方向定向。 每个模具相对于剩余的骰子在第二方向上通过相应的横向偏移距离而在第二方向上侧向偏移，使得每个模具的焊盘不会在垂直于衬底的方向上设置在衬底和剩余骰子的任何部分之间。 多个接合线将接合焊盘连接到衬底。 还公开了半导体器件的制造方法。

公开(公告)号：USRE46819E1

公开(公告)日：2018-05-01

申请号：US14141686

申请日：2013-12-27

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Peter Gillingham ,  Robert McKenzie

IPC: G06F13/42 ,  G11C29/50 ,  G11C7/10

CPC classification number: G06F13/4243 ,  G11C7/1066 ,  G11C29/50012 ,  G11C2207/2254

Abstract: A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up. Another embodiment of the invention is a simple, low latency clock domain crossing circuit based on the DQS latched sample of the counter.

公开(公告)号：US09190369B2

公开(公告)日：2015-11-17

申请号：US14254865

申请日：2014-04-16

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Peter Gillingham

IPC: H01L21/02 ,  H01L23/00 ,  G11C5/02 ,  G11C5/06 ,  H01L23/48 ,  H01L23/544 ,  H01L25/065 ,  H01L21/82 ,  H03K17/00 ,  H01L23/528

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C5/06 ,  H01L21/02697 ,  H01L21/82 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/544 ,  H01L24/03 ,  H01L24/16 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/14 ,  H03K17/00 ,  H01L2924/00

Abstract: In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

Abstract translation: 在适用于互连IC堆叠的集成电路（IC）中，除了不间断的TSV之外，还提供了中断的通硅通孔（TSV）。 中断的TSV提供除了堆栈的IC之间的公共并行路径之外的信号路径。 这允许使用TSV实现IC识别方案和其他功能，而不需要堆叠的替代IC的角旋转。