公开(公告)号：US4241425A

公开(公告)日：1980-12-23

申请号：US10839

申请日：1979-02-09

申请人： Ronald P. Cenker ,  Donald G. Clemons ,  William R. Huber, III ,  Frank J. Procyk

发明人： Ronald P. Cenker ,  Donald G. Clemons ,  William R. Huber, III ,  Frank J. Procyk

IPC分类号： G11C11/34 ,  G11C11/406 ,  G11C11/4063 ,  G11C11/408 ,  G11C11/40

CPC分类号： G11C11/408 ,  G11C11/406 ,  G11C11/4063

摘要： An MOS dynamic random access memory (RAM) includes an array of memory cells arranged in rows and columns. The array is divided into two or more sub-arrays. In an operating cycle where a cell is being accessed for reading and/or writing, only the sub-array containing the accessed cell is fully selected while the other sub-arrays are partially selected. A fully selected sub-array is one in which both a row and a column are selected, whereas in a partially selected sub-array, only a row is selected. In the partially selected sub-array where only refreshing of the cells in the selected row takes place, the column decoders and drivers remain inactive throughout the memory cycle.

摘要翻译： MOS动态随机存取存储器（RAM）包括以行和列排列的存储器单元阵列。 阵列分为两个或更多个子阵列。 在读取和/或写入单元格的操作周期中，只有包含被访问单元格的子阵列被完全选择，而其他子阵列被部分选择。 完全选择的子数组是选择行和列的子数组，而在部分选择的子数组中，只选择一行。 在部分选择的子阵列中，只有刷新所选行中的单元格，列解码器和驱动器在整个存储器周期中保持不活动。

公开(公告)号：US4222112A

公开(公告)日：1980-09-09

申请号：US10741

申请日：1979-02-09

申请人： Donald G. Clemons ,  Frank J. Procyk

发明人： Donald G. Clemons ,  Frank J. Procyk

IPC分类号： G11C7/00 ,  G11C11/34 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4063 ,  G11C11/4091 ,  G11C7/02

CPC分类号： G11C11/4091 ,  G11C11/404 ,  G11C11/4063

摘要： An MOS dynamic random access memory (RAM) includes an array of memory cells arranged in rows and columns. The array is divided into two or more sub-arrays. During an operating cycle latching of the sense amplifiers in the sub-arrays is staggered to avoid coincidence of current peaks each arising when the sense amplifiers in one of the sub-arrays are simultaneously latched. Latching takes place first in a sub-array in which a cell is selected. Recovery of the column conductors in the sub-arrays is also staggered to avoid coincidence of current peaks each occurring when one of the sub-arrays is recovered. The sub-array in which a cell is selected is recovered last.

摘要翻译： MOS动态随机存取存储器（RAM）包括以行和列排列的存储器单元阵列。 阵列分为两个或更多个子阵列。 在操作周期期间，子阵列中的读出放大器的锁存是交错的，以避免当一个子阵列中的读出放大器同时锁存时出现的当前峰值的一致。 首先在选择单元格的子阵列中进行锁存。 子阵列中的列导体的恢复也是交错的，以避免当其中一个子阵列被恢复时出现的当前峰值的一致。 最后恢复选择单元格的子阵列。

公开(公告)号：US4494220A

公开(公告)日：1985-01-15

申请号：US444239

申请日：1982-11-24

申请人： Austin C. Dumbri ,  Frank J. Procyk

发明人： Austin C. Dumbri ,  Frank J. Procyk

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

CPC分类号： G11C29/787 ,  G11C29/838

摘要： A folded bit line configured DRAM, with standard even and odd rows of memory cells, also includes spare even and odd rows of memory cells which can be substituted for standard rows found to have defective cells or interconnections. Each of the decoders associated with a standard row includes provision for being disconnected if found to be associated with a defective row. One common spare decoder is associated with one spare even and one spare odd row of memory cells. Each spare decoder is designed normally to be deselected for any address but to be able to assume the address of any disconnected standard row. Disconnection of a standard decoder and substitution of a spare decoder with the appropriate even or odd row are made possible by appropriate inclusion of fusible links which are selectively opened by laser irradiation. The use of one spare decoder with both an even and odd row serves to reduce the number of needed spare decoders and thus reduces overall chip size.

摘要翻译： 具有标准偶数行和奇数行存储器单元的折叠位线配置的DRAM还包括备用偶数和奇数行的存储器单元，其可以替代发现具有缺陷单元或互连的标准行。 与标准行相关联的每个解码器包括如果发现与缺陷行相关联的断开的设置。 一个常见的备用解码器与一个备用偶数和一个备用奇数行的存储器单元相关联。 每个备用解码器通常设计为取消任何地址的选择，但能够承担任何断开的标准行的地址。 通过适当地包括通过激光照射选择性地打开的可熔链路，使得标准解码器的断开和具有适当的偶数或奇数行的备用解码器的替代成为可能。 使用具有偶数和奇数行的一个备用解码器用于减少所需备用解码器的数量，从而减少整体芯片尺寸。

公开(公告)号：US4567581A

公开(公告)日：1986-01-28

申请号：US452156

申请日：1982-12-22

申请人： Austin C. Dumbri ,  Frank J. Procyk

发明人： Austin C. Dumbri ,  Frank J. Procyk

IPC分类号： G11C8/00 ,  G11C8/10 ,  G11C11/40

CPC分类号： G11C8/10 ,  G11C8/00

摘要： A memory having multiplexed address inputs uses a column decoder which is deactivated during row address time and becomes activated during column address time. Access time and power dissipation are reduced since the column decoder need not be fully recovered after row address information has terminated and column address information is available.

摘要翻译： 具有复用地址输入的存储器使用列解码器，其在行地址时间期间被去激活，并且在列地址时间期间被激活。 降低了访问时间和功耗，因为行地址信息已经终止并且列地址信息可用后，列解码器不需要完全恢复。

公开(公告)号：US4228528A

公开(公告)日：1980-10-14

申请号：US10739

申请日：1979-02-09

申请人： Ronald P. Cenker ,  Frank J. Procyk

发明人： Ronald P. Cenker ,  Frank J. Procyk

IPC分类号： G11C11/34 ,  G06F11/20 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C29/781

摘要： A memory is provided with standard rows and columns and spare rows and columns for substitution for standard rows and columns found to have defective cells. Each of the decoders associated with a standard row and/or column includes provision for being disconnected if found to be associated with a defective row or column. Each of the decoders associated with a spare row and/or column is designed normally to be deselected for any address but to be able to assume the address of any disconnected row or column. Disconnection of the standard decoders and substitution of the spare decoders are made possible by appropriate inclusion of fusible links which can be selectively opened by laser irradiation.

摘要翻译： 为内存提供标准行和列以及备用行和列，用于替代发现有缺陷单元格的标准行和列。 与标准行和/或列相关联的每个解码器包括如果发现与有缺陷的行或列相关联的断开的设置。 与备用行和/或列相关联的每个解码器被设计为通常被取消选择用于任何地址，但是能够承担任何断开的行或列的地址。 标准解码器的断开和备用解码器的替代可以通过适当地包括可以通过激光照射选择性地打开的可熔链路成为可能。

公开(公告)号：US4541078A

公开(公告)日：1985-09-10

申请号：US452155

申请日：1982-12-22

申请人： Austin C. Dumbri ,  Frank J. Procyk

发明人： Austin C. Dumbri ,  Frank J. Procyk

IPC分类号： G11C8/00 ,  G11C8/10 ,  G11C11/40

CPC分类号： G11C8/00 ,  G11C8/10

摘要： A memory of rows and columns of memory cells uses a multiplexed input address buffer having output row-column address lines which are coupled to a multiplexer and to column decoders. The multiplexer is coupled to row address decoders and serves to selectively couple the address lines to the row decoders. The address lines typically first carry row address information and then column address information. The use of a common portion of the address lines to couple the address buffer to the column decoders and multiplexer tends to reduce the overall size of the memory and thereby increases yield and reduces cost.

摘要翻译： 存储器单元的行和列的存储器使用具有耦合到多路复用器和列解码器的输出行列地址线的多路复用输入地址缓冲器。 多路复用器耦合到行地址解码器，并用于选择性地将地址线耦合到行解码器。 地址线通常首先携带行地址信息，然后传送列地址信息。 使用地址线的公共部分将地址缓冲器耦合到列解码器和多路复用器倾向于减小存储器的总体大小，从而增加产量并降低成本。

公开(公告)号：US4240195A

公开(公告)日：1980-12-23

申请号：US942861

申请日：1978-09-15

申请人： James T. Clemens ,  John D. Cuthbert ,  Frank J. Procyk ,  George M. Trout

发明人： James T. Clemens ,  John D. Cuthbert ,  Frank J. Procyk ,  George M. Trout

IPC分类号： G11C14/00 ,  G11C11/40 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/535 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  B01J17/00

CPC分类号： H01L27/10844 ,  H01L21/768 ,  H01L23/535 ,  H01L27/10805 ,  H01L2924/0002

摘要： A memory in which each cell comprises an MOS transistor merged with a storage capacitor and in which the cells are arranged to permit adjacent pairs of transistors in a common column to share a common source and the transistors in a common row to share a common gate electrode conductor. The memory uses a first polycrystalline silicon layer which is patterned to provide interconnected storage electrodes and a second polycrystalline silicon layer which is patterned to provide a plurality of stripes to serve as the bit sense lines and a plurality of gate electrodes.

摘要翻译： 一种存储器，其中每个单元包括与存储电容器合并的MOS晶体管，其中所述单元被布置成允许公共列中的相邻晶体管共享公共源，并且共用行中的晶体管共享公共栅电极 导体。 存储器使用图案化以提供互连的存储电极的第一多晶硅层和被图案化以提供多个条纹以用作位感测线和多个栅电极的第二多晶硅层。

公开(公告)号：US4679172A

公开(公告)日：1987-07-07

申请号：US738664

申请日：1985-05-28

申请人： Howard C. Kirsch ,  Frank J. Procyk

发明人： Howard C. Kirsch ,  Frank J. Procyk

IPC分类号： G11C11/409 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C11/4094 ,  G11C11/406

摘要： A dynamic memory obtains reduced leakage currents through the access transistors by preventing the low-going column conductors from reaching zero volts for at least a majority of the duration of the active portion of a memory cycle. The low-going conductors are allowed to reach zero volts during the refresh operation. One advantage is a possible increase in the data storage time between required refresh operations. An increase in the refresh interval is especially useful for memory operations wherein a multiplicity of columns are selected for a given row selection. The present technique also addresses the tendency toward increased sub-threshold leakage as field effect transistor thresholds decrease.

摘要翻译： 动态存储器通过防止低位列导体在存储器周期的有效部分的持续时间的至少大部分时间内达到零伏特来获得通过存取晶体管的减小的漏电流。 在刷新操作期间，低导体允许达到零伏特。 一个优点是可能增加所需的刷新操作之间的数据存储时间。 刷新间隔的增加对于对于给定行选择选择多个列的存储器操作特别有用。 本技术还解决了随着场效应晶体管阈值下降而增加的次阈值泄漏的趋势。

公开(公告)号：US4542483A

公开(公告)日：1985-09-17

申请号：US557632

申请日：1983-12-02

申请人： Frank J. Procyk

发明人： Frank J. Procyk

IPC分类号： G11C11/4091 ,  G11C11/40

CPC分类号： G11C11/4091

摘要： The present invention relates to the inclusion of an additional sense amplifier (100) on each column of a dynamic random access memory (RAM). The second sense amplifier is located near the input/output (DQ) line and functions to increase the rate of discharge of the selected column pair (C.sub.n, C.sub.n) thereby improving the transfer of logic information from a selected memory cell (M) to the input/output line associated therewith. The second sense amplifier in the column of the selected memory cell is activated by the same pulse (CCDQ) which connects the selected column to the input/output line, where only the second sense amplifier associated with the accessed column is activated during a single read/write cycle.

摘要翻译： 本发明涉及在动态随机存取存储器（RAM）的每一列上包括附加的读出放大器（100）。 第二读出放大器位于输入/输出（DQ）线附近，并且用于增加所选列对（Cn，＆amp; upbar＆Cn）的放电速率，从而改善逻辑信息从所选存储单元（M）到 与其相关联的输入/输出线。 所选存储单元的列中的第二读出放大器由连接所选列到输入/输出线的相同脉冲（CCDQ）激活，其中在单次读取期间仅激活与访问列相关联的第二读出放大器 /写周期。