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    Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
    1.
    发明申请
    Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain 失效
    具有嵌入式SiGe源极/漏极的假晶Si / SiGe / Si体器件

    公开(公告)号：US20070196987A1

    公开(公告)日：2007-08-23

    申请号：US11358483

    申请日：2006-02-21

    申请人： Dureseti Chidambarrao ,  Anda Mocuta ,  Dan Mocuta ,  Carl Radens

    发明人： Dureseti Chidambarrao ,  Anda Mocuta ,  Dan Mocuta ,  Carl Radens

    IPC分类号： H01L21/336

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.

    摘要翻译： 本发明涉及半导体结构和制造方法，更具体地说涉及在PFET的源极/漏极区域中具有至少一个嵌入的SiGe层以及在NFET的沟道区域中至少一个嵌入的SiGe层的CMOS器件。 在一个实施方案中，本发明的结构增强了NFET器件中的电子迁移率，并进一步提高了PFET器件中的空穴迁移率。 此外，通过使用制造方法并因此实现本发明的最终结构，还可以在同一衬底上构造每个具有嵌入的SiGe层的PFET和NFET。

    SILICON/SILCION GERMANINUM/SILICON BODY DEVICE WITH EMBEDDED CARBON DOPANT
    4.
    发明申请
    SILICON/SILCION GERMANINUM/SILICON BODY DEVICE WITH EMBEDDED CARBON DOPANT 失效
    含硅碳化硅的硅/硅石/硅体器件

    公开(公告)号：US20070257249A1

    公开(公告)日：2007-11-08

    申请号：US11381810

    申请日：2006-05-05

    申请人： Anda Mocuta ,  Dureseti Chidambarrao ,  Ricardo Donaton ,  David Onsongo ,  Kern Rim

    发明人： Anda Mocuta ,  Dureseti Chidambarrao ,  Ricardo Donaton ,  David Onsongo ,  Kern Rim

    IPC分类号： H01L31/00

    CPC分类号： H01L21/823807 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78687

    摘要： A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.

    摘要翻译： 一种制造半导体器件的半导体结构和方法，特别是NFET器件。 这些装置包括在应力诱导层上提供的应力接收层，其中在其间的界面处的材料减少了结构中失配位错的发生和传播。 应力接收层是硅（Si），应力诱导层是硅锗（SiGe），并且材料是在形成器件期间通过掺杂层提供的碳。 也可以在整个SiGe层中掺杂碳。

    STRUCTURE AND METHOD FOR MANUFACTURING MOSFET WITH SUPER-STEEP RETROGRADED ISLAND
    5.
    发明申请
    STRUCTURE AND METHOD FOR MANUFACTURING MOSFET WITH SUPER-STEEP RETROGRADED ISLAND 失效
    具有超级退化岛的MOSFET制造结构和方法

    公开(公告)号：US20070252203A1

    公开(公告)日：2007-11-01

    申请号：US11774221

    申请日：2007-07-06

    申请人： Huilong Zhu ,  Effendi Leobandung ,  Anda Mocuta ,  Dan Mocuta

    发明人： Huilong Zhu ,  Effendi Leobandung ,  Anda Mocuta ,  Dan Mocuta

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7842 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

    摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffisivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

    摘要翻译： 本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。 低扩散层可以是Si 1-xy X z Z z，其中Z可以是碳（C），氙（Xe）， 锗（Ge），氪（Kr），氩（Ar），氮（N）或其组合。

    Structure and method for manufacturing MOSFET with super-steep retrograded island
    6.
    发明申请
    Structure and method for manufacturing MOSFET with super-steep retrograded island 失效
    具有超陡退化岛的MOSFET的制造和制造方法

    公开(公告)号：US20060068555A1

    公开(公告)日：2006-03-30

    申请号：US10954838

    申请日：2004-09-30

    申请人： Huilong Zhu ,  Effendi Leobandung ,  Anda Mocuta ,  Dan Mocuta

    发明人： Huilong Zhu ,  Effendi Leobandung ,  Anda Mocuta ,  Dan Mocuta

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7842 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

    摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

    摘要翻译： 本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。 低扩散性层可以是Si 1-xy X z Z z，其中Z可以是碳（C），氙（Xe）， 锗（Ge），氪（Kr），氩（Ar），氮（N）或其组合。

    Method for preventing sidewall consumption during oxidation of SGOI islands
    7.
    发明申请
    Method for preventing sidewall consumption during oxidation of SGOI islands 失效

    公开(公告)号：US20060063358A1

    公开(公告)日：2006-03-23

    申请号：US10943354

    申请日：2004-09-17

    申请人： Stephen Bedell ,  Anda Mocuta

    发明人： Stephen Bedell ,  Anda Mocuta

    IPC分类号： H01L21/20 ,  H01L21/31

    CPC分类号： H01L21/32105 ,  H01L21/84 ,  Y10S438/967

    摘要： A method of forming a substantially relaxed SiGe-on-insulator substrate in which the consumption of the sidewalls of SiGe-containing island structures during a high temperature relaxation annealing is substantially prevented or eliminated is provided. The method serves to maintain the original lateral dimensions of the patterned SiGe-containing islands, while providing a uniform and homogeneous Ge fraction of the islands that is independent of each island size. The method includes forming an oxidation mask on at least sidewalls of a SiGe-containing island structure that is located on a barrier layer that is resistant to Ge diffusion. A heating step is then employed to cause at least relaxation within the SiGe-containing island structure. The presence of the oxidation mask substantially prevents consumption of at least the sidewalls of the SiGe-containing island structure during the heating step.

    SEMICONDUCTOR DEVICE FORMING METHOD AND STRUCTURE FOR RETARDING DOPANT-ENHANCED DIFFUSION
    8.
    发明申请
    SEMICONDUCTOR DEVICE FORMING METHOD AND STRUCTURE FOR RETARDING DOPANT-ENHANCED DIFFUSION 审中-公开
    半导体器件形成方法和结构

    公开(公告)号：US20060220112A1

    公开(公告)日：2006-10-05

    申请号：US10907464

    申请日：2005-04-01

    申请人： Huilong Zhu ,  Kam-Leung Lee ,  Jinghong Li ,  Anda Mocuta

    发明人： Huilong Zhu ,  Kam-Leung Lee ,  Jinghong Li ,  Anda Mocuta

    IPC分类号： H01L29/76

    CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L29/1054

    摘要： Methods and structure formed for retarding diffusion of a dopant into a channel of a strained Si—SiGe CMOS device are disclosed. The methods form a diffusion retardant region in a substrate including at least one diffusion retardant species such as xenon (Xe), and then form a channel layer over the diffusion retardant region. Each step is conducted prior to formation of a gate on the substrate. As a result, if necessary, the diffusion retardant region can be annealed and cleaned or etched to remove defects in the substrate to reduce external resistance and leakage of devices. The diffusion retardant region positioned under the channel slows down the diffusion of a dopant, e.g., arsenic (As). The invention is also applicable to other substrates.

    摘要翻译： 公开了用于将掺杂剂扩散到应变Si-SiGe CMOS器件的沟道中的方法和结构。 该方法在包括至少一种扩散阻挡物质如氙（Xe）的基板中形成扩散阻挡区，然后在扩散阻挡区上形成通道层。 每个步骤在基板上形成栅极之前进行。 结果，如果需要，可以对扩散阻挡区域进行退火和清洁或蚀刻以去除衬底中的缺陷，以减少器件的外部电阻和漏电。 位于通道下方的扩散阻滞区减慢了掺杂剂（例如砷）（As）的扩散。 本发明也适用于其它基材。