公开(公告)号：US10242942B2

公开(公告)日：2019-03-26

申请号：US15127708

申请日：2014-04-25

申请人： Mathew J. Manusharow ,  Dustin P. Wood ,  Debendra Mallik

发明人： Mathew J. Manusharow ,  Dustin P. Wood ,  Debendra Mallik

IPC分类号： H01L23/48 ,  H01L23/50 ,  H01L23/00 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/525

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.

公开(公告)号：US09526175B2

公开(公告)日：2016-12-20

申请号：US13996830

申请日：2012-04-24

申请人： Mathew J. Manusharow ,  Mihir K. Roy ,  Kaladhar Radhakrishnan ,  Debendra Mallik ,  Edward A. Burton

发明人： Mathew J. Manusharow ,  Mihir K. Roy ,  Kaladhar Radhakrishnan ,  Debendra Mallik ,  Edward A. Burton

IPC分类号： H05K1/18 ,  H05K1/14 ,  H01L23/13 ,  H05K1/11 ,  H01L23/50

CPC分类号： H05K1/183 ,  H01L23/13 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19104 ,  H01L2924/19106 ,  H05K1/111 ,  H05K1/141 ,  H05K2201/1003

摘要： The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate have an opening, wherein the opening may be formed through the microelectronic substrate or may be a recess formed in the microelectronic substrate. A microelectronic package may be attached to the microelectronic substrate, wherein the microelectronic package may include an interposer having a first surface and an opposing second surface. A microelectronic device may be attached to the interposer first surface and the interposer may be attached to the microelectronic substrate by the interposer first surface such that the microelectronic device extends into the opening. At least one secondary microelectronic device may be attached to the interposer second surface.

摘要翻译： 本说明书涉及制造微电子结构的领域。 微电子结构可以包括具有开口的微电子衬底，其中开口可以通过微电子衬底形成，或者可以是在微电子衬底中形成的凹部。 微电子封装可以附接到微电子衬底，其中微电子封装可以包括具有第一表面和相对的第二表面的插入件。 微电子器件可以附接到插入器第一表面，并且插入器可以通过插入器第一表面附接到微电子衬底，使得微电子器件延伸到开口中。 至少一个次级微电子器件可以附接到插入件第二表面。

公开(公告)号：US20140251669A1

公开(公告)日：2014-09-11

申请号：US13996830

申请日：2012-04-24

申请人： Mathew J. Manusharow ,  Mihir K. Roy ,  Kaladhar Radhakrishnan ,  Debendra Mallik ,  Edward A. Burton

发明人： Mathew J. Manusharow ,  Mihir K. Roy ,  Kaladhar Radhakrishnan ,  Debendra Mallik ,  Edward A. Burton

IPC分类号： H05K1/18 ,  H05K1/11

CPC分类号： H05K1/183 ,  H01L23/13 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19104 ,  H01L2924/19106 ,  H05K1/111 ,  H05K1/141 ,  H05K2201/1003

摘要： The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate have an opening, wherein the opening may be formed through the microelectronic substrate or may be a recess formed in the microelectronic substrate. A microelectronic package may be attached to the microelectronic substrate, wherein the microelectronic package may include an interposer having a first surface and an opposing second surface. A microelectronic device may be attached to the interposer first surface and the interposer may be attached to the microelectronic substrate by the interposer first surface such that the microelectronic device extends into the opening. At least one secondary microelectronic device may be attached to the interposer second surface.

摘要翻译： 本说明书涉及制造微电子结构的领域。 微电子结构可以包括具有开口的微电子衬底，其中开口可以通过微电子衬底形成，或者可以是在微电子衬底中形成的凹部。 微电子封装可以附接到微电子衬底，其中微电子封装可以包括具有第一表面和相对的第二表面的插入件。 微电子器件可以附接到插入器第一表面，并且插入器可以通过插入器第一表面附接到微电子衬底，使得微电子器件延伸到开口中。 至少一个次级微电子器件可以附接到插入件第二表面。

公开(公告)号：US20130270691A1

公开(公告)日：2013-10-17

申请号：US13976098

申请日：2011-12-16

申请人： Debendra Mallik ,  Sridhar Narasimhan ,  Mathew J. Manusharow ,  Thomas A. Boyd

发明人： Debendra Mallik ,  Sridhar Narasimhan ,  Mathew J. Manusharow ,  Thomas A. Boyd

IPC分类号： H01L23/34 ,  H01L21/50

CPC分类号： H01L23/34 ,  H01L21/50 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49833 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01327 ,  H01L2924/00

摘要： A package for a microelectronic die (110) includes a first substrate (120) adjacent to a first surface (112) of the die, a second substrate (130) adjacent to the first substrate, and a heat spreader (140) adjacent to a second surface (111) of the die. The heat spreader makes contact with both the first substrate and the second substrate.

摘要翻译： 用于微电子管芯（110）的封装包括邻近管芯的第一表面（112）的第一衬底（120），与第一衬底相邻的第二衬底（130）和邻近第一衬底的散热器 模具的第二表面（111）。 散热器与第一基板和第二基板接触。

公开(公告)号：US08901748B2

公开(公告)日：2014-12-02

申请号：US13828947

申请日：2013-03-14

申请人： Mathew J. Manusharow ,  Debendra Mallik

发明人： Mathew J. Manusharow ,  Debendra Mallik

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/34 ,  H01L23/02 ,  H01L23/58 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L24/82 ,  H01L23/36 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/20 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00

摘要： An external direct connection usable for an embedded interconnect bridge package is described. In one example, a package has a substrate, a first semiconductor die having a first bridge interconnect region, and a second semiconductor die having a second bridge interconnect region. The package has a bridge embedded in the substrate, the bridge having a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region, and an external connection rail extending between the interconnect bridge and the first and second semiconductor dies to supply external connection to the first and second bridge interconnect regions.

摘要翻译： 描述可用于嵌入式互连桥式封装的外部直接连接。 在一个示例中，封装具有基板，具有第一桥接互连区域的第一半导体管芯和具有第二桥接互连区域的第二半导体管芯。 所述封装具有嵌入在所述基板中的桥，所述桥具有用于连接到所述第一桥互连区域的第一接触区域和用于连接到所述第二桥接互连区域的第二接触区域，以及在所述互连桥和 所述第一和第二半导体管芯提供到所述第一和第二桥互连区域的外部连接。

公开(公告)号：US20140264791A1

公开(公告)日：2014-09-18

申请号：US13828947

申请日：2013-03-14

申请人： MATHEW J. MANUSHAROW ,  Debendra Mallik

发明人： MATHEW J. MANUSHAROW ,  Debendra Mallik

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L24/82 ,  H01L23/36 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/20 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00

摘要： An external direct connection usable for an embedded interconnect bridge package is described. In one example, a package has a substrate, a first semiconductor die having a first bridge interconnect region, and a second semiconductor die having a second bridge interconnect region. The package has a bridge embedded in the substrate, the bridge having a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region, and an external connection rail extending between the interconnect bridge and the first and second semiconductor dies to supply external connection to the first and second bridge interconnect regions.

摘要翻译： 描述可用于嵌入式互连桥式封装的外部直接连接。 在一个示例中，封装具有基板，具有第一桥接互连区域的第一半导体管芯和具有第二桥接互连区域的第二半导体管芯。 所述封装具有嵌入在所述基板中的桥，所述桥具有用于连接到所述第一桥互连区域的第一接触区域和用于连接到所述第二桥接互连区域的第二接触区域，以及在所述互连桥和 所述第一和第二半导体管芯提供到所述第一和第二桥互连区域的外部连接。

公开(公告)号：US09478476B2

公开(公告)日：2016-10-25

申请号：US13976098

申请日：2011-12-16

申请人： Debendra Mallik ,  Sridhar Narasimhan ,  Mathew J. Manusharow ,  Thomas A. Boyd

发明人： Debendra Mallik ,  Sridhar Narasimhan ,  Mathew J. Manusharow ,  Thomas A. Boyd

IPC分类号： H01L23/48 ,  H01L23/34 ,  H01L23/36 ,  H01L21/50 ,  H01L23/367 ,  H01L23/42 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/34 ,  H01L21/50 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49833 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01327 ,  H01L2924/00

摘要： A package for a microelectronic die (110) includes a first substrate (120) adjacent to a first surface (112) of the die, a second substrate (130) adjacent to the first substrate, and a heat spreader (140) adjacent to a second surface (111) of the die. The heat spreader makes contact with both the first substrate and the second substrate.

摘要翻译： 用于微电子管芯（110）的封装包括邻近管芯的第一表面（112）的第一衬底（120），与第一衬底相邻的第二衬底（130）和邻近第一衬底的散热器 模具的第二表面（111）。 散热器与第一基板和第二基板接触。

公开(公告)号：US07321172B2

公开(公告)日：2008-01-22

申请号：US11227532

申请日：2005-09-14

申请人： Dustin P. Wood ,  Debendra Mallik

发明人： Dustin P. Wood ,  Debendra Mallik

IPC分类号： H01L23/48

CPC分类号： H01L23/498 ,  H01L21/4846 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K3/242 ,  H05K3/243 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/073

摘要： In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

摘要翻译： 在一个实施例中，公开了一种包括提供具有第一焊盘和第二焊盘的半导体焊盘封装的方法。 使用第一工艺将包含第一金属的第一层沉积在第一焊盘上。 然后使用第二工艺将第二金属沉积在第一焊盘和第一层上。 在另一个实施例中，第一工艺包括电镀工艺，第二工艺包括直接浸金（DIG）工艺。 在另一实施例中，第一焊盘是电源或接地焊盘，第二焊盘是信号焊盘。

公开(公告)号：US07186645B2

公开(公告)日：2007-03-06

申请号：US10685171

申请日：2003-10-13

申请人： Dustin P. Wood ,  Debendra Mallik

发明人： Dustin P. Wood ,  Debendra Mallik

IPC分类号： H01L21/44

CPC分类号： H01L23/498 ,  H01L21/4846 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K3/242 ,  H05K3/243 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/073

摘要： In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

摘要翻译： 在一个实施例中，公开了一种包括提供具有第一焊盘和第二焊盘的半导体焊盘封装的方法。 使用第一工艺将包含第一金属的第一层沉积在第一焊盘上。 然后使用第二工艺将第二金属沉积在第一焊盘和第一层上。 在另一个实施例中，第一工艺包括电镀工艺，第二工艺包括直接浸金（DIG）工艺。 在另一实施例中，第一焊盘是电源或接地焊盘，第二焊盘是信号焊盘。

公开(公告)号：US09530758B2

公开(公告)日：2016-12-27

申请号：US14750811

申请日：2015-06-25

申请人： Debendra Mallik ,  Robert L. Sankman

发明人： Debendra Mallik ,  Robert L. Sankman

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18

CPC分类号： H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/82 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/051 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81986 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/01079 ,  H01L2224/11

摘要： 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.