公开(公告)号：US20150177309A1

公开(公告)日：2015-06-25

申请号：US14302354

申请日：2014-06-11

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Jong Min LEE ,  Chull Won JU ,  Byoung Gue MIN

IPC分类号： G01R31/26 ,  G01R31/28

CPC分类号： G01R31/2621 ,  G01R31/2608

摘要： A test device includes: a testing unit connected with a measurement line, and configured to apply bias to the measurement line and measure the measurement line; a plurality of switching units configured to electrically connect the measurement line and the plurality of samples; and a control unit configured to sequentially turn on the plurality of switching units to sequentially apply the bias to the plurality of samples. The control unit determines whether a corresponding device sample has a defect based on a first measurement value according to measurement by the testing unit when the bias is applied to each of the plurality of samples.

摘要翻译： 测试装置包括：测试单元，与测量线连接，并被配置为向测量线施加偏压并测量测量线; 多个开关单元，被配置为电连接所述测量线和所述多个样本; 以及控制单元，被配置为顺序地接通所述多个开关单元以将所述偏置顺序地施加到所述多个样本。 当偏置被应用于多个样本中的每一个时，控制单元根据测试单元的测量，基于第一测量值来确定对应的设备样本是否具有缺陷。

公开(公告)号：US20150236108A1

公开(公告)日：2015-08-20

申请号：US14328247

申请日：2014-07-10

申请人： Electronics and Telecommunications Research Institute

发明人： Seong Il KIM ,  Dong Min KANG ,  Sang Heung LEE ,  Ho Kyun AHN ,  Hyung Sup YOON ,  Byoung Gue MIN ,  Jong Won LIM

IPC分类号： H01L29/423 ,  H01L21/283 ,  H01L29/778

CPC分类号： H01L29/42312 ,  H01L21/28114 ,  H01L21/28587 ,  H01L21/28593 ,  H01L29/42316 ,  H01L29/66863 ,  H01L29/778 ,  H01L29/812

摘要： Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 μm or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.

摘要翻译： 公开了一种具有稳定的栅极结构的半导体器件及其制造方法，其中通过在栅极头的宽度方向上的栅极头附近还包括多个栅极脚来稳定栅极结构，以作为支撑体 在包括具有0.2μm或更小的长度的精细栅极脚的栅极结构中，并且栅极头具有预定尺寸。 因此，可以防止半导体器件的栅电极塌陷，并且在半导体器件的处理期间或之后提高半导体器件的可靠性。

公开(公告)号：US20150206847A1

公开(公告)日：2015-07-23

申请号：US14453969

申请日：2014-08-07

申请人： Electronics and Telecommunications Research Institute

发明人： Hae Cheon KIM ,  Ho Kyun AHN ,  Byoung Gue MIN ,  Hyung Sup YOON ,  Jong Won LIM

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0225 ,  H01L2224/03466 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/1033 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1423 ,  H01L2924/201 ,  H01L2924/37001 ,  H01L2224/45099

摘要： The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.

摘要翻译： 本发明涉及一种GaN晶体管及其制造方法，其中通过在源极，漏极和栅极的焊盘的边缘处形成欧姆金属层来改善焊盘的结构，因此 适于引线接合或背面通孔形成工艺。 因此，通过在制造GaN晶体管期间在焊盘的边缘处形成欧姆金属，可以增强焊盘的金属层与GaN基板之间的粘合力， 接合或背面通孔形成工艺，并提高器件的可靠性。

公开(公告)号：US20150380482A1

公开(公告)日：2015-12-31

申请号：US14658121

申请日：2015-03-13

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Ho Kyun AHN ,  Hae Cheon KIM ,  Jong Won LIM ,  Dong Min KANG ,  Yong Hwan KWON ,  SEONG IL KIM ,  Zin Sig KIM ,  Eun Soo NAM ,  Byoung Gue MIN ,  Hyung Sup YOON ,  Kyung Ho LEE ,  Jong Min LEE ,  Kyu Jun CHO

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L21/28 ,  H01L29/49 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/31 ,  H01L29/778 ,  H01L29/45

CPC分类号： H01L21/28264 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786

摘要： Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.

摘要翻译： 本文提供了包括基板的半导体器件; 形成在所述基板的顶部上的有源层; 形成在所述有源层的顶部上并具有第一孔的保护层; 源电极，形成在保护层顶部的驱动栅电极和漏电极; 以及形成在所述第一孔的顶部上的第一附加栅电极，其中由于施加到所述源电极，漏电极和驱动栅电极中的每一个的电压，向所述有源层，保护层和驱动栅电极施加电场， 并且第一附加栅电极被配置为衰减施加到有源层，保护层和驱动栅电极的至少一部分的电场的尺寸。

公开(公告)号：US20150194494A1

公开(公告)日：2015-07-09

申请号：US14243322

申请日：2014-04-02

申请人： Electronics and Telecommunications Research Institute

发明人： Ho Kyun AHN ,  Hae Cheon KIM ,  Zin Sig KIM ,  Sang Heung LEE ,  Byoung Gue MIN ,  Hyung Sup YOON ,  Dong Min KANG ,  Seong Il KIM ,  Jong Min LEE ,  Jong Won LIM ,  Yong Hwan KWON ,  Eun Soo NAM

IPC分类号： H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/402 ,  H01L21/283 ,  H01L21/28593 ,  H01L29/2003 ,  H01L29/42312 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7787

摘要： Disclosed are a field effect transistor for high voltage driving including a gate electrode structure in which a gate head extended in a direction of a drain is supported by a field plate embedded under a region of the gate head so as to achieve high voltage driving, and a manufacturing method thereof. Accordingly, the gate head extended in the direction of the drain is supported by the field plate electrically spaced by using an insulating layer, so that it is possible to stably manufacture a gate electrode including the extended gate head, and gate resistance is decreased by the gate head extended in the direction of the drain and an electric field peak value between the gate and the drain is decreased by the gate electrode including the gate head extended in the direction of the drain and the field plate proximate to the gate, thereby achieving an effect in that a breakdown voltage of a device is increased.

摘要翻译： 公开了一种用于高电压驱动的场效应晶体管，其包括栅极电极结构，其中在漏极方向上延伸的栅极头由嵌入在栅极头的区域内的场板支撑以实现高电压驱动，以及 其制造方法。 因此，在漏极方向上延伸的栅极头通过使用绝缘层而被电隔离的场板支撑，使得可以稳定地制造包括延伸栅极头的栅电极，并且栅极电阻通过 栅极头在漏极的方向上延伸，栅极和漏极之间的电场峰值由包括在漏极方向上延伸的栅极和靠近栅极的场板的栅电极减小，由此实现 效果是器件的击穿电压增加。

公开(公告)号：US20150144961A1

公开(公告)日：2015-05-28

申请号：US14175452

申请日：2014-02-07

申请人： Electronics and Telecommunications Research Institute

发明人： Hyung Sup YOON ,  Byoung Gue MIN ,  Ho Kyun AHN ,  Jong Won LIM ,  Dong Min KANG ,  Jong Min LEE

IPC分类号： H01L29/778 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786

摘要： A high frequency device includes: a capping layer formed on an epitaxial structure; source and drain electrodes formed on the capping layer; a multilayer insulating pattern formed on entire surfaces of the source and drain electrodes and the capping layer in a step shape; a T-shaped gate passing through the multilayer insulating pattern and the capping layer to be in contact with the epitaxial structure; and a passivation layer formed along entire surfaces of the T-shaped gate and the multilayer insulating pattern.

摘要翻译： 高频器件包括：形成在外延结构上的覆盖层; 源极和漏极形成在覆盖层上; 形成在所述源电极和漏电极以及所述覆盖层的整个表面上的阶梯形状的多层绝缘图案; 通过所述多层绝缘图案和所述覆盖层与所述外延结构接触的T形栅极; 以及在T形栅极和多层绝缘图案的整个表面上形成的钝化层。