公开(公告)号：US06671865B1

公开(公告)日：2003-12-30

申请号：US09994567

申请日：2001-11-27

申请人： Anwar Ali ,  Farshad Ghahghahi ,  Edwin M. Fulcher

发明人： Anwar Ali ,  Farshad Ghahghahi ,  Edwin M. Fulcher

IPC分类号： G06F1750

CPC分类号： H01L23/49838 ,  G06F17/5068 ,  G06F2217/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： An input/output array of an integrated circuit comprises concentric rings of input/output tiles. The peripheral input/output tiles are adjacently arranged along the periphery of the integrated circuit to form a peripheral ring. Each of the peripheral input/output tiles is associated with a corresponding peripheral input/output device group having x1 number of input/output devices. Each peripheral input/output tile includes x1 number of signal contacts for coupling signals to corresponding ones of the x1 number of input/output devices, y1 number of input/output driver voltage contacts for coupling a source voltage to drivers of the x1 number of input/output devices, and z1 number of ground contacts. The interior input/output tiles are adjacently arranged within the interior of the integrated circuit to form n number of substantially concentric interior rings, where n is greater than or equal to one.

摘要翻译： 集成电路的输入/输出阵列包括输入/​​输出瓦片的同心环。 周边输入/输出瓦片沿着集成电路的周边相邻布置以形成外围环。 每个外围输入/输出瓦片与具有x1个输入/输出设备的相应的外围输入/输出设备组相关联。 每个外围输入/输出瓦片包括x1个信号触点，用于将信号耦合到x1个输入/输出设备中的相应的输入/输出设备，y1个输入/输出驱动器电压触点数量，用于将源电压耦合到X1输入端的驱动器 /输出设备，以及z1个接地点数。 内部输入/输出瓦片相邻地布置在集成电路的内部，以形成n个基本上同心的内部环，其中n大于或等于1。

公开(公告)号：US06744130B1

公开(公告)日：2004-06-01

申请号：US10615063

申请日：2003-07-08

申请人： Leah M. Miller ,  Aritharan Thurairajaratnam ,  Edwin M. Fulcher

发明人： Leah M. Miller ,  Aritharan Thurairajaratnam ,  Edwin M. Fulcher

IPC分类号： H01L2348

CPC分类号： H05K1/0245 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/16 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09627 ,  H05K2201/09663

摘要： A package substrate having separate routing layers for transmitter signals and receiver signals, which signals are routed in differential pairs. The differential pairs of signal routing lines are isolated between a separate ground plane for transmitter and receiver traces and dedicated power planes, where a single power plane is dedicated to a single differential pair of signal routing lines. In this manner, a high degree of electrical isolation exists not only between the transmitter signal traces and the receiver signal traces, which are on different layers, but also between different differential pairs of signal routing lines on the same layer, each of which has its own dedicated power plane. Thus, a very high speed core routing system can be designed in a package substrate that can then be adapted as necessary to support a broad range of different integrated circuit designs.

摘要翻译： 封装衬底具有用于发射机信号和接收机信号的分离的路由层，哪些信号以差分对路由。 信号路由线路的差分对在用于发射器和接收器迹线的独立接地平面和专用功率平面之间隔离，其中单个功率平面专用于单个差分信号路由线路对。 以这种方式，高度的电隔离不仅存在于发射机信号迹线和位于不同层上的接收机信号迹线之间，而且存在于同一层上的信号路由线路的不同差分对之间， 自有专用电源机。 因此，可以在封装衬底中设计非常高速的芯路由系统，然后可以根据需要进行调整，以支持各种不同的集成电路设计。

公开(公告)号：US06867488B2

公开(公告)日：2005-03-15

申请号：US10304974

申请日：2002-11-26

申请人： Edwin M. Fulcher

发明人： Edwin M. Fulcher

IPC分类号： H01L23/528 ,  H01L23/52

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit having signal traces, power traces, and ground traces. The signal traces are disposed on at least one signal distribution layer, and the signal traces on the at least one signal distribution layer are formed at no more than a first thickness. The power traces and ground traces are formed on at least one power ground distribution layer, where the at least one power ground distribution layer is an overlying layer of the integrated circuit relative to the at least one signal distribution layer. The power traces and ground traces on the at least one power ground distribution layer are formed at no less than a second thickness that is greater than the first thickness of the signal traces. In this manner, the signal traces, which can be formed with a relatively thin thickness, can be placed very close together on the signal distribution layers, and have sufficient conductivity for the signals transmitted thereon. At the same time, the power and ground traces, which are typically required to carry a greater current, can be formed with a relatively thick thickness and with wider widths, without taking up precious space on the signal distribution layers. In this manner, the signal traces can be placed closed together, both because they are thinner and because space is not taken by power and ground traces on the same layer, and thus they require less space, and the integrated circuit can be made smaller.

摘要翻译： 具有信号迹线，功率迹线和接地迹线的集成电路。 信号迹线设置在至少一个信号分布层上，并且至少一个信号分布层上的信号迹线形成在不超过第一厚度。 功率迹线和接地迹线形成在至少一个电力接地分布层上，其中至少一个电力接地分布层是相对于至少一个信号分布层的集成电路的上层。 在至少一个功率接地分布层上的功率迹线和接地迹线形成在不小于信号迹线的第一厚度的第二厚度上。 以这种方式，可以形成有相对薄的厚度的信号迹线可以非常靠近在一起放置在信号分布层上，并且对于在其上传输的信号具有足够的导电性。 同时，通常需要承载更大电流的电源和接地迹线可以以相对较厚的厚度和较宽的宽度形成，而不会在信号分布层上占据宝贵的空间。 以这种方式，信号迹线可以被放置在一起，因为它们更薄，并且由于空间不被同一层上的电力和接地迹线占用，因此它们需要更少的空间，并且可以使集成电路更小。

公开(公告)号：US06828643B2

公开(公告)日：2004-12-07

申请号：US10287668

申请日：2002-11-04

申请人： Edwin M. Fulcher

发明人： Edwin M. Fulcher

IPC分类号： H01L3100

CPC分类号： H01L24/06 ,  H01L21/76838 ,  H01L23/5286 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/00014

摘要： An integrated circuit having functional circuitry within a core portion of the integrated circuit. Input circuits are disposed on a first layer within a peripheral portion of the integrated circuit, where the input circuits are electrically connected to the functional circuitry. Power and ground buss lines are disposed on a second layer within the peripheral portion of the integrated circuit, where the second layer overlies the first layer. The power and ground buss lines overlie the input circuits, and are electrically connected to the input circuits. Bonding pads are disposed on a third layer within the peripheral portion of the integrated circuit, where the third layer overlies the second layer. The bonding pads overlie the power and ground buss lines and the input circuits, and are electrically connected to the input circuits.

公开(公告)号：US06459049B1

公开(公告)日：2002-10-01

申请号：US09885299

申请日：2001-06-20

申请人： Leah M. Miller ,  Farshad Ghahghahi ,  Edwin M. Fulcher ,  Aritharan Thurairajaratnam

发明人： Leah M. Miller ,  Farshad Ghahghahi ,  Edwin M. Fulcher ,  Aritharan Thurairajaratnam

IPC分类号： H01R909

CPC分类号： H05K1/0216 ,  H01R31/06 ,  H05K1/112 ,  H05K1/117 ,  H05K2201/09236 ,  H05K2201/09281 ,  H05K2201/09727

摘要： A structure for receiving electrical signals near a central portion of the structure and distributing the electrical signals to a peripheral portion of the structure. The structure has a first set of contacts arranged in an array near the central portion of the structure. Electrically conductive traces connect the first set of contacts to a second set of contacts, where each of the electrically conductive traces has at least a first segment, a second segment, and a third segment. The first segment of each of the electrically conductive traces has relatively narrow width and spacing. The first segment of each of the electrically conductive traces is connected on a first end of the first segment to one of the first set of contacts and on a second end of the first segment to the second segment of each of the electrically conductive traces. The second segment of each of the electrically conductive traces has relatively intermediate width and spacing. The second segment of each of the electrically conductive traces is connected on a first end of the second segment to the second end of the first segment and on a second end of the second segment to the third segment of each of the electrically conductive traces. The third segment of each of the electrically conductive traces has relatively wide width and spacing. The third segment of each of the electrically conductive traces is connected on a first end of the third segment to the second end of the second segment and on a second end of the third segment to one of the second set of contacts.

摘要翻译： 一种用于在所述结构的中心部分附近接收电信号并将所述电信号分配到所述结构的外围部分的结构。 该结构具有靠近结构的中心部分排列成阵列的第一组触点。 导电迹线将第一组触点连接到第二组触点，其中每个导电迹线具有至少第一段，第二段和第三段。 每个导电迹线的第一段具有相对较窄的宽度和间隔。 每个导电迹线的第一段在第一段的第一端连接到第一组触点中的一个，并且在第一段的第二端连接到每个导电迹线的第二段。 每个导电迹线的第二段具有相对中间的宽度和间隔。 每个导电迹线的第二段在第二段的第一端连接到第一段的第二端，并且在第二段的第二端连接到每个导电迹线的第三段。 每个导电迹线的第三段具有相对宽的宽度和间隔。 每个导电迹线的第三段在第三段的第一端连接到第二段的第二端，并且在第三段的第二端连接到第二组接触中的一个。

公开(公告)号：US06963129B1

公开(公告)日：2005-11-08

申请号：US10464178

申请日：2003-06-18

申请人： Thomas Evans ,  Stan Mihelcic ,  Leah M. Miller ,  Kumar Nagarajan ,  Edwin M. Fulcher

发明人： Thomas Evans ,  Stan Mihelcic ,  Leah M. Miller ,  Kumar Nagarajan ,  Edwin M. Fulcher

IPC分类号： H01L23/10 ,  H01L23/34 ,  H01L23/36 ,  H01L25/065

CPC分类号： H01L23/36 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/19105

摘要： A system and method are provided for forming a multi-chip package. The multi-chip package includes a multi-layer substrate and a heat spreader of single, unibody construction. At least two integrated circuits are coupled between the multi-layer substrate and the heat spreader. The integrated circuits are spaced from one another to allow airflow between those circuits and a portion of the underside surface of the heat spreader. Depending on the layout of the package, a passive device can also be placed in the space between integrated circuits. The passive device extends upward a spaced distance from the underneath surface of the heat spreader so as not to block the airflow therebetween. The multi-chip package can accommodate integrated circuits that are either all packaged, all unpackaged, or a combination of each. If packaged and unpackaged integrated circuits are placed on the multi-layer substrate, the heat spreader can extend in two separate planes to accommodate the different thicknesses of those packaged and unpackaged integrated circuits. Alternatively, a second heat spreader can be placed on a relatively thin integrated circuit so that the upper surface of the second heat spreader is coplanar with an upper surface of a relatively thick integrated circuit. This will allow a planar heat spreader to be arranged across the thick integrated circuit and the second heat spreader. In all instances, however, the heat spreader extends as a single, contiguous unibody element across the entire multi-chip package.

摘要翻译： 提供了一种用于形成多芯片封装的系统和方法。 多芯片封装包括多层基板和单一单体结构的散热器。 至少两个集成电路耦合在多层基板和散热器之间。 集成电路彼此间隔开，以允许这些电路之间的气流和散热器的下表面的一部分。 根据封装的布局，无源器件也可放置在集成电路之间的空间中。 被动装置从散热器的下表面向上延伸一定距离，以便不阻挡散热器之间的气流。 多芯片封装可以容纳所有封装，所有未封装的封装或各自的组合的集成电路。 如果封装和未封装的集成电路放置在多层基板上，散热器可以在两个独立的平面中延伸，以适应那些封装和未封装的集成电路的不同厚度。 或者，可以将第二散热器放置在相对薄的集成电路上，使得第二散热器的上表面与相对较厚的集成电路的上表面共面。 这将允许平面散热器布置在厚集成电路和第二散热器之间。 然而，在所有情况下，散热器在整个多芯片封装上延伸为单个，连续的一体元件。

公开(公告)号：US06798035B1

公开(公告)日：2004-09-28

申请号：US10600255

申请日：2003-06-20

申请人： Qwai H. Low ,  Ramaswamy Ranganathan ,  Edwin M. Fulcher

发明人： Qwai H. Low ,  Ramaswamy Ranganathan ,  Edwin M. Fulcher

IPC分类号： H01L3100

CPC分类号： H01L24/05 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00

摘要： A bonding pad structure having an electrically conductive capping layer. An electrically conductive first supporting layer is disposed immediately under the electrically conductive capping layer, without any intervening layers between the electrically conductive capping layer and the electrically conductive first supporting layer. The electrically conductive first supporting layer is configured as one of a sheet having no voids and a sheet having slotted voids in a first direction. An electrically conductive second supporting layer is disposed under the electrically conductive first supporting layer. The electrically conductive second supporting layer is configured as one of a sheet having slotted voids in the first direction, a sheet having slotted voids in a second direction, and a sheet having checkerboard voids.

摘要翻译： 一种具有导电覆盖层的焊盘结构。 导电的第一支撑层设置在导电覆盖层的正下方，在导电覆盖层和导电的第一支撑层之间没有任何中间层。 导电性第一支撑层被构造为没有空隙的片材之一和在第一方向上具有开槽空隙的片材。 导电的第二支撑层设置在导电的第一支撑层之下。 导电性第二支撑层被构造为在第一方向上具有开槽空隙的片材之一，在第二方向上具有开槽空隙的片材和具有棋盘空隙的片材。

公开(公告)号：US06791177B1

公开(公告)日：2004-09-14

申请号：US10435805

申请日：2003-05-12

申请人： Leah M. Miller ,  Aritharan Thurairajaratnam ,  Edwin M. Fulcher

发明人： Leah M. Miller ,  Aritharan Thurairajaratnam ,  Edwin M. Fulcher

IPC分类号： H01L2352

CPC分类号： H05K1/0219 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K2201/09236 ,  H05K2201/09618 ,  H01L2924/00

摘要： A package substrate is contemplated herein for reducing cross-talk for noise-sensitive signals. The package substrate includes noise-sensitive conductors adapted to receive the noise-sensitive signals. In one embodiment, the cross-sectional width of the noise-sensitive conductors is increased to reduce certain parasitic effects such as resistance and/or inductance. The package substrate also includes guard conductors which are arranged co-planar with and substantially parallel to the noise-sensitive conductors. A plurality of vias spaced equidistant from one another extends from a ground conductor to the guard conductors, providing a substantially uniform voltage across the guard conductors. The overall effect will reduce the inductive and capacitive cross-talk from neighboring signals and increase the signal integrity of noise-sensitive signals.

摘要翻译： 本文考虑的封装衬底用于减少噪声敏感信号的串扰。 封装衬底包括适于接收噪声敏感信号的噪声敏感导体。 在一个实施例中，噪声敏感导体的横截面宽度增加以减少某些寄生效应，例如电阻和/或电感。 封装衬底还包括与噪声敏感导体共面并基本上平行的保护导体。 彼此间隔开等距的多个通孔从接地导体延伸到保护导体，从而在保护导体上提供基本均匀的电压。 整体效果将减少相邻信号的电感和电容串扰，并增加噪声敏感信号的信号完整性。

公开(公告)号：US06762366B1

公开(公告)日：2004-07-13

申请号：US09844530

申请日：2001-04-27

申请人： Leah M. Miller ,  Farshad Ghahghahi ,  Edwin M. Fulcher

发明人： Leah M. Miller ,  Farshad Ghahghahi ,  Edwin M. Fulcher

IPC分类号： H05K100

CPC分类号： H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/15173 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： A printed circuit board having contacts in a contact array of rows and columns. Groups of n columns of the contacts are electrically connected to n−1 columns of vias disposed interstitially in a via array between the n columns of the contacts. A major vertical routing channel is formed between adjacent groups of n columns of the contacts and the n−1 columns of vias. First electrical traces are electrically connected to a first number of the vias. The first electrical traces are routed to an outside edge of the via array through the major vertical routing channel.

摘要翻译： 具有行和列的接触阵列中的触点的印刷电路板。 触点的n列的组电连接到间隙地布置在接触件的n列之间的通孔阵列中的n-1列通孔。 主要的垂直布线通道形成在相邻的n列的触点组和n-1列的通孔之间。 第一电迹线与第一数目的通孔电连接。 第一电迹线通过主垂直路由通道路由到通孔阵列的外边缘。

公开(公告)号：US6008534A

公开(公告)日：1999-12-28

申请号：US6813

申请日：1998-01-14

申请人： Edwin M. Fulcher

发明人： Edwin M. Fulcher

IPC分类号： H01L23/498 ,  H01L23/66 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/66 ,  H01L23/49822 ,  H01L2223/6616 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011

摘要： A semiconductor device package is presented having signal traces interposed between power and ground conductors in order to form stripline transmission lines. The semiconductor device package includes a substrate having a die area defined upon an upper surface. The die area is dimensioned to receive the integrated circuit. A first planar conductive layer formed upon the upper surface includes a first set of bonding pads and a set of conductive traces. Members of the first set of bonding pads are arranged upon the upper surface proximate the die area, and are used to make electrical connections to the integrated circuit. Members of the set of conductive traces are connected between one of two polarities of a power supply and corresponding members of the first set of bonding pads, and function as reference planes for underlying signal traces. A second planar conductive layer is positioned between the first planar conductive layer and an underside surface of the substrate. The second conductive layer is connected to the other of the two polarities of the power supply, and also functions as a reference plane for signal traces within the substrate. A planar conductive signal layer is interposed between the first and second conductive layers and patterned to form a set of signal traces. The signal traces form stripline transmission lines which are highly desirable in high frequency applications as their impedances are highly predictable and controllable.

摘要翻译： 呈现在电源和接地导体之间插入信号迹线以形成带状线传输线的半导体器件封装。 半导体器件封装包括具有限定在上表面上的管芯区域的衬底。 管芯区域的尺寸用于接收集成电路。 形成在上表面上的第一平面导电层包括第一组接合焊盘和一组导电迹线。 第一组接合焊盘的部件布置在靠近管芯区域的上表面上，并用于与集成电路进行电连接。 一组导电迹线的成员连接在电源的两个极性之一和第一组接合焊盘的相应部件之间，并且用作下面的信号迹线的参考平面。 第二平面导电层位于第一平面导电层和衬底的下表面之间。 第二导电层连接到电源的两个极性中的另一个，并且还用作衬底内的信号迹线的参考平面。 平面导电信号层插入在第一和第二导电层之间并被图案化以形成一组信号迹线。 信号迹线形成在高频应用中非常需要的带状线传输线，因为它们的阻抗是高度可预测的和可控的。