Automatic layer deposition process
    1.
    发明申请
    Automatic layer deposition process 审中-公开
    自动层沉积工艺

    公开(公告)号:US20070161180A1

    公开(公告)日:2007-07-12

    申请号:US11331441

    申请日:2006-01-13

    IPC分类号: H01L21/8242

    摘要: The atomic layer deposition process according to the invention provides the following steps for the production of homogeneous layers on a substrate. The substrate is introduced into a reaction chamber. A first precursor is introduced into the reaction chamber, which first precursor reacts on the surface of the substrate to form an intermediate product. A second precursor is introduced into the reaction chamber, which second precursor has a low sticking coefficient and reacts with part of the intermediate product to form a first product. A third precursor is introduced into the reaction chamber, which third precursor has a high sticking coefficient and reacts with the remaining part of the intermediate product to form a second product. The second precursor and its first product reduce the effective sticking coefficient of the third precursor by partially covering the surface.

    摘要翻译: 根据本发明的原子层沉积方法提供了在基底上生产均质层的以下步骤。 将基底引入反应室。 将第一前体引入反应室,其中第一前体在基材的表面上反应形成中间产物。 将第二前体引入反应室,该第二前体具有低粘附系数并与部分中间产物反应以形成第一产物。 将第三前体引入反应室,该第三前体具有高粘附系数并与中间产物的剩余部分反应以形成第二产物。 第二种前体及其第一种产物通过部分覆盖表面来降低第三种前体的有效粘附系数。

    METHOD, APPARATUS AND STARTING MATERIAL FOR PROVIDING A GASEOUS PRECURSOR
    2.
    发明申请
    METHOD, APPARATUS AND STARTING MATERIAL FOR PROVIDING A GASEOUS PRECURSOR 审中-公开
    方法,装置和起始材料,用于提供气体前体

    公开(公告)号:US20070269598A1

    公开(公告)日:2007-11-22

    申请号:US11750073

    申请日:2007-05-17

    IPC分类号: C23C16/00

    CPC分类号: C23C16/4481 C23C16/08

    摘要: A method and apparatus for providing a gaseous precursor for a coating process. A starting material having a pulverulent precursor material is heated in order to cause a vaporization of the pulverulent precursor material, whereby a gaseous precursor is produced. A carrier gas is flowed past the starting material at a distance minimizing or preventing a convective gas flow, while transporting the gaseous precursor to a processing region containing a wafer to be coated.

    摘要翻译: 一种用于提供涂覆工艺的气态前体的方法和装置。 加热具有粉状前体材料的起始材料,以便引起粉状前体材料的汽化,由此产生气态前体。 在将气态前体输送到包含待涂覆的晶片的处理区域的同时,载气以一定距离流过原料,使其最小化或防止对流气体流动。

    METHOD FOR FORMING A DIELECTRIC LAYER
    3.
    发明申请
    METHOD FOR FORMING A DIELECTRIC LAYER 审中-公开
    形成介电层的方法

    公开(公告)号:US20080176375A1

    公开(公告)日:2008-07-24

    申请号:US11970654

    申请日:2008-01-08

    IPC分类号: H01L21/31 H01L21/02

    摘要: The present invention relates to a deposition of a dielectric layer. On a substrate having a structured area a crystallization seed layer for a dielectric layer is deposited via an atomic layer deposition technique employing a first and a second precursor on the structured area of the substrate. The first pre-cursor is a compound having the constitutional formula M1(R1Cp)x(R2)4-x, wherein M1 is one of hafnium and zirconium, Cp is cyclopentadienyl, R1 is independently selected of methyl, ethyl and alkyl, R2 is independently selected of hydrogen, methyl, ethyl, alkyl and alkoxyl, and x is one or two. The dielectric layer is deposited on the crystallization seed layer via an atomic layer deposition technique employing a third and a forth precursor wherein the third pre-cursor being a compound having the constitutional formula M2 R3 R4 R5 R6, wherein M2 is one of hafnium or zirconium and R3, R4, R5, and R6 are independently selected of alkyl amines.

    摘要翻译: 本发明涉及电介质层的沉积。 在具有结构区域的基板上,通过使用第一和第二前体的原子层沉积技术在基板的结构化区域上沉积用于电介质层的结晶种子层。 第一个前体是具有结构式M 1(R 1)的化合物,其中R 1,R 2,R 2, 其中M 1是铪和锆中的一种,Cp是环戊二烯基,R 1独立地选自甲基,乙基 和烷基,R 2独立地选自氢,甲基,乙基,烷基和烷氧基,x是一个或两个。 介电层通过使用第三和第四前体的原子层沉积技术沉积在结晶种子层上,其中第三个前体是具有结构式M 2 O 3的化合物 其中M 2是铪或锆中的一种,R 2是R 5 R 4,R 5,R 6和R 6独立地选自烷基胺。

    Methods for fabricating integrated circuits with narrow, metal filled openings
    5.
    发明授权
    Methods for fabricating integrated circuits with narrow, metal filled openings 有权
    用于制造具有窄的金属填充开口的集成电路的方法

    公开(公告)号:US08652890B2

    公开(公告)日:2014-02-18

    申请号:US13408291

    申请日:2012-02-29

    IPC分类号: H01L21/338

    摘要: Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode.

    摘要翻译: 提供了用于制造包括金属填充的窄开口的集成电路的方法。 根据一个实施例,一种方法包括形成覆盖半导体衬底的虚拟栅极,随后去除虚拟栅极以形成窄的开口。 在半导体衬底上沉积一层高介电常数绝缘体和一层功函数确定材料。 工作层功能确定材料暴露于第一室中的氮气环境。 在氮气环境的存在下,将钛层沉积在第一室中的窄开口中,以使钛层的第一部分被氮化。 钛的沉积继续,并且钛层的剩余部分沉积为基本上纯的钛。 沉积铝覆盖在钛层上以填充窄开口并形成栅电极。

    Methods for fabricating integrated circuits with controlled P-channel threshold voltage
    6.
    发明授权
    Methods for fabricating integrated circuits with controlled P-channel threshold voltage 有权
    用于制造具有受控P沟道阈值电压的集成电路的方法

    公开(公告)号:US08420519B1

    公开(公告)日:2013-04-16

    申请号:US13286292

    申请日:2011-11-01

    IPC分类号: H01L21/283

    摘要: Methods are provided for fabricating integrated circuits having controlled threshold voltages. In accordance with one embodiment a method includes forming a gate dielectric overlying an N-doped silicon substrate and depositing a layer of titanium nitride and a layer of tantalum nitride overlying the gate dielectric. A sub-monolayer of tantalum oxide is deposited overlying the layer of tantalum nitride by a process of atomic layer deposition, and oxygen is diffused from the tantalum oxide through the tantalum nitride and titanium nitride.

    摘要翻译: 提供了用于制造具有受控阈值电压的集成电路的方法。 根据一个实施例,一种方法包括形成覆盖在N掺杂硅衬底上的栅极电介质,并且沉积氮化钛层和覆盖在栅极电介质上的氮化钽层。 氧化钽的亚单层通过原子层沉积的过程沉积在氮化钽层上,并且氧从钽氧化物扩散通过氮化钽和氮化钛。

    PASSIVATING POINT DEFECTS IN HIGH-K GATE DIELECTRIC LAYERS DURING GATE STACK FORMATION
    7.
    发明申请
    PASSIVATING POINT DEFECTS IN HIGH-K GATE DIELECTRIC LAYERS DURING GATE STACK FORMATION 有权
    栅格堆叠形成过程中高K栅介质层的钝点缺陷

    公开(公告)号:US20130267086A1

    公开(公告)日:2013-10-10

    申请号:US13439016

    申请日:2012-04-04

    IPC分类号: H01L21/28 H01L21/31

    摘要: Generally, the present disclosure is directed to techniques for improving the reliability of semiconductor devices with high-k gate dielectric layers by passivating point defects during the gate stack formation. One illustrative method disclosed herein includes performing a plurality of material deposition cycles to form a high-k dielectric layer above a semiconductor material layer, and introducing a passivating material into a gaseous precursor that is used for forming the high-k dielectric layer during at least one of the plurality of material deposition cycles.

    摘要翻译: 通常,本公开涉及用于通过在栅极堆叠形成期间的钝化点缺陷来提高具有高k栅极电介质层的半导体器件的可靠性的技术。 本文公开的一种说明性方法包括执行多个材料沉积循环以在半导体材料层上方形成高k电介质层,以及将钝化材料引入到用于在至少形成高k介电层的气态前体中 多个材料沉积循环中的一个。

    METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CONTROLLED P-CHANNEL THRESHOLD VOLTAGE
    8.
    发明申请
    METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CONTROLLED P-CHANNEL THRESHOLD VOLTAGE 有权
    用控制的P通道阈值电压制造集成电路的方法

    公开(公告)号:US20130109166A1

    公开(公告)日:2013-05-02

    申请号:US13286292

    申请日:2011-11-01

    IPC分类号: H01L21/28

    摘要: Methods are provided for fabricating integrated circuits having controlled threshold voltages. In accordance with one embodiment a method includes forming a gate dielectric overlying an N-doped silicon substrate and depositing a layer of titanium nitride and a layer of tantalum nitride overlying the gate dielectric. A sub-monolayer of tantalum oxide is deposited overlying the layer of tantalum nitride by a process of atomic layer deposition, and oxygen is diffused from the tantalum oxide through the tantalum nitride and titanium nitride.

    摘要翻译: 提供了用于制造具有受控阈值电压的集成电路的方法。 根据一个实施例,一种方法包括形成覆盖在N掺杂硅衬底上的栅极电介质,并且沉积氮化钛层和覆盖在栅极电介质上的氮化钽层。 氧化钽的亚单层通过原子层沉积的过程沉积在氮化钽层上,并且氧从钽氧化物扩散通过氮化钽和氮化钛。