公开(公告)号：US20130003158A1

公开(公告)日：2013-01-03

申请号：US13171245

申请日：2011-06-28

申请人： Evgeni Gousev ,  Russell Wayne Gruhlke

发明人： Evgeni Gousev ,  Russell Wayne Gruhlke

IPC分类号： G02B26/00 ,  B05D3/00 ,  B23P11/00 ,  B05D5/06

CPC分类号： G02B26/001 ,  Y10T29/49826

摘要： This disclosure provides apparatus, systems and methods for optical decoupling. In one implementation, an optical system includes a substrate transmissive to visible light, a first antireflective structure disposed on a surface of the substrate, a second antireflective structure. The first and second antireflective structures define at least one cavity containing air in between. The optical system further includes a plurality of support posts configured to space the first antireflective structure from the second antireflective structure to define the height of the at least one cavity. A reflective display is disposed on a surface of the second antireflective structure opposite the at least one cavity.

摘要翻译： 本公开提供了用于光学去耦的装置，系统和方法。 在一个实施方案中，光学系统包括透射可见光的衬底，设置在衬底的表面上的第一抗反射结构，第二抗反射结构。 第一和第二抗反射结构限定了至少一个容纳空气的空腔。 光学系统还包括多个支撑柱，其被配置为将第一抗反射结构与第二抗反射结构间隔开以限定至少一个腔的高度。 反射显示器设置在与至少一个空腔相对的第二抗反射结构的表面上。

公开(公告)号：US20120274647A1

公开(公告)日：2012-11-01

申请号：US13094687

申请日：2011-04-26

申请人： Je-Hsiung Lan ,  Sang-June Park ,  Jonghae Kim ,  Evgeni Gousev ,  Matthew Nowak ,  Philip J. Stephanou ,  Justin Black ,  Kurt Petersen ,  Srinivasan Ganapathi

发明人： Je-Hsiung Lan ,  Sang-June Park ,  Jonghae Kim ,  Evgeni Gousev ,  Matthew Nowak ,  Philip J. Stephanou ,  Justin Black ,  Kurt Petersen ,  Srinivasan Ganapathi

IPC分类号： H01L41/053 ,  G09G5/39 ,  H01L41/22 ,  G06T1/60

CPC分类号： H03H3/0072 ,  H03H9/2447 ,  Y10T29/42

摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a sacrificial layer is deposited on an insulating substrate. A lower electrode layer is formed proximate the sacrificial layer. A piezoelectric layer is deposited on the lower electrode layer. An upper electrode layer is formed on the piezoelectric layer. At least a portion of the sacrificial layer is removed to define a cavity such that at least a portion of the lower electrode layer is spaced apart from the insulating substrate.

摘要翻译： 本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。 在一个方面，牺牲层沉积在绝缘衬底上。 在牺牲层附近形成下电极层。 压电层沉积在下电极层上。 在压电层上形成上电极层。 去除牺牲层的至少一部分以限定空腔，使得下电极层的至少一部分与绝缘基板间隔开。

公开(公告)号：US20120206462A1

公开(公告)日：2012-08-16

申请号：US13453844

申请日：2012-04-23

申请人： Ana R. Londergan ,  Bangalore R. Natarajan ,  Evgeni Gousev ,  James Randolph Webster ,  David Heald

发明人： Ana R. Londergan ,  Bangalore R. Natarajan ,  Evgeni Gousev ,  James Randolph Webster ,  David Heald

IPC分类号： G02B26/00 ,  B05D5/06 ,  G06T1/00

CPC分类号： G02B26/001 ,  B81B3/0008 ,  B81B2201/047

摘要： Devices, methods, and systems comprising a MEMS device, for example, an interferometric modulator, that comprises a cavity in which a layer coats multiple surfaces. The layer is conformal or non-conformal. In some embodiments, the layer is formed by atomic layer deposition (ALD). Preferably, the layer comprises a dielectric material. In some embodiments, the MEMS device also exhibits improved characteristics, such as improved electrical insulation between moving electrodes, reduced stiction, and/or improved mechanical properties.

摘要翻译： 包括MEMS器件（例如干涉式调制器）的器件，方法和系统，其包括其中层涂覆多个表面的空腔。 该层是保形的或非保形的。 在一些实施例中，该层由原子层沉积（ALD）形成。 优选地，该层包括电介质材料。 在一些实施例中，MEMS器件还表现出改进的特性，例如移动电极之间的改善的电绝缘性，降低的静摩擦力和/或改善的机械性能。

公开(公告)号：US08164815B2

公开(公告)日：2012-04-24

申请号：US12795294

申请日：2010-06-07

申请人： Ana R. Londergan ,  Bangalore R. Natarajan ,  Evgeni Gousev ,  James Randolph Webster ,  David Heald

发明人： Ana R. Londergan ,  Bangalore R. Natarajan ,  Evgeni Gousev ,  James Randolph Webster ,  David Heald

IPC分类号： G02F1/00

CPC分类号： G02B26/001 ,  B81B3/0008 ,  B81B2201/047

摘要： Devices, methods, and systems comprising a MEMS device, for example, an interferometric modulator, that comprises a cavity in which a layer coats multiple surfaces. The layer is conformal or non-conformal. In some embodiments, the layer is formed by atomic layer deposition (ALD). Preferably, the layer comprises a dielectric material. In some embodiments, the MEMS device also exhibits improved characteristics, such as improved electrical insulation between moving electrodes, reduced stiction, and/or improved mechanical properties.

摘要翻译： 包括MEMS器件（例如干涉式调制器）的器件，方法和系统，其包括其中层涂覆多个表面的空腔。 该层是保形的或非保形的。 在一些实施例中，该层由原子层沉积（ALD）形成。 优选地，该层包括电介质材料。 在一些实施例中，MEMS器件还表现出改进的特性，例如移动电极之间的改善的电绝缘性，降低的静摩擦力和/或改善的机械性能。

公开(公告)号：US20110128212A1

公开(公告)日：2011-06-02

申请号：US12629456

申请日：2009-12-02

申请人： Manish Kothari ,  Evgeni Gousev ,  Russel Allyn Martin

发明人： Manish Kothari ,  Evgeni Gousev ,  Russel Allyn Martin

IPC分类号： G09G3/32 ,  G09G3/20 ,  G09G3/36 ,  G01P15/00

CPC分类号： G02B26/001 ,  G02B26/0841

摘要： A display device having an illumination system with integrated accelerometer is disclosed in which a portion of the illumination system is used as the proof mass for the accelerometer. In one embodiment, the display device includes a plurality of display elements, one or more light sources, one or more light redirectors configured to redirect at least a portion of the light generated by the light sources to at least a portion of the plurality of display elements, one or more light detectors each configured to determine a light intensity, and a processor configured to determine one or more accelerations based on the determined light intensity.

摘要翻译： 公开了具有集成加速度计的照明系统的显示装置，其中照明系统的一部分被用作加速度计的检验质量块。 在一个实施例中，显示设备包括多个显示元件，一个或多个光源，一个或多个光重定向器，其配置成将由光源产生的光的至少一部分重定向到多个显示器的至少一部分 元件，每个被配置为确定光强度的一个或多个光检测器以及被配置为基于所确定的光强度来确定一个或多个加速度的处理器。

公开(公告)号：US07566664B2

公开(公告)日：2009-07-28

申请号：US11497726

申请日：2006-08-02

申请人： Xiaoming Yan ,  Brian Arbuckle ,  Evgeni Gousev ,  Ming-Hau Tung

发明人： Xiaoming Yan ,  Brian Arbuckle ,  Evgeni Gousev ,  Ming-Hau Tung

IPC分类号： H01L21/20

CPC分类号： G02B26/001 ,  B81B2201/047 ,  B81C1/00595 ,  B81C2201/0132

摘要： A method for etching a target material in the presence of a structural material with improved selectivity uses a vapor phase etchant and a co-etchant. Embodiments of the method exhibit improved selectivities of from at least about 2-times to at least about 100-times compared with a similar etching process not using a co-etchant. In some embodiments, the target material comprises a metal etchable by the vapor phase etchant. Embodiments of the method are particularly useful in the manufacture of MEMS devices, for example, interferometric modulators. In some embodiments, the target material comprises a metal etchable by the vapor phase etchant, for example, molybdenum and the structural material comprises a dielectric, for example silicon dioxide.

摘要翻译： 在具有改进的选择性的结构材料存在下蚀刻靶材料的方法使用气相蚀刻剂和共蚀刻剂。 与不使用共蚀刻剂的类似蚀刻工艺相比，该方法的实施例表现出从至少约2倍至至少约100倍的改进的选择性。 在一些实施例中，靶材料包括可由气相蚀刻剂蚀刻的金属。 该方法的实施例在MEMS器件（例如干涉式调制器）的制造中特别有用。 在一些实施例中，靶材料包括可由气相蚀刻剂（例如，钼）蚀刻的金属，并且结构材料包括电介质，例如二氧化硅。

公开(公告)号：US20090122384A1

公开(公告)日：2009-05-14

申请号：US11938673

申请日：2007-11-12

申请人： Daniel Felnhofer ,  Evgeni Gousev

发明人： Daniel Felnhofer ,  Evgeni Gousev

IPC分类号： G02B26/02 ,  G02F1/21 ,  H01H57/00 ,  B05D5/12 ,  H01L21/36

CPC分类号： B81B3/0086 ,  B81B2201/045 ,  G02B26/001 ,  G11C23/00

摘要： A capacitive MEMS device is formed having a material between electrodes that traps and retains charges. The material can be realized in several configurations. It can be a multilayer dielectric stack with regions of different band gap energies or band energy levels. The dielectric materials can be trappy itself, i.e. when defects or trap sites are pre-fabricated in the material. Another configuration involves a thin layer of a conductive material with the energy level in the forbidden gap of the dielectric layer. The device may be programmed (i.e. offset and threshold voltages pre-set) by a method making advantageous use of charge storage in the material, wherein the interferometric modulator is pre-charged in such a way that the hysteresis curve shifts, and the actuation voltage threshold of the modulator is significantly lowered. During programming phase, charge transfer between the electrodes and the materials can be performed by applying voltage to the electrodes (i.e. applying electrical field across the material) or by UV-illumination and injection of electrical charges over the energy barrier. The interferometric modulator may then be retained in an actuated state with a significantly lower actuation voltage, thereby saving power.

摘要翻译： 形成电容MEMS器件，其具有陷阱并保持电荷的电极之间的材料。 该材料可以在几种配置中实现。 它可以是具有不同带隙能量或带能级的区域的多层电介质叠层。 电介质材料本身可以是歪斜的，即当在材料中预先制造缺陷或捕获位置时。 另一种结构涉及导电材料的薄层，其中电介质层的禁止间隙具有能级。 可以通过有利地使用材料中的电荷存储的方法来对器件进行编程（即，偏移和阈值电压预设），其中干涉式调制器以滞后曲线偏移的方式预充电，并且致动电压 调制器的阈值显着降低。 在编程阶段期间，电极和材料之间的电荷转移可以通过向电极施加电压（即跨越材料施加电场）或通过UV照射和在能量屏障上注入电荷来执行。 然后干涉式调制器可以以明显更低的致动电压保持在致动状态，从而节省功率。

公开(公告)号：US20090071933A1

公开(公告)日：2009-03-19

申请号：US12210026

申请日：2008-09-12

申请人： Philip Floyd ,  Evgeni Gousev ,  David Heald ,  Ben Ward Hertzler ,  Chok Ho ,  Teruo Sasagawa ,  Xiaoming Yan ,  Todd Lyle Zion

发明人： Philip Floyd ,  Evgeni Gousev ,  David Heald ,  Ben Ward Hertzler ,  Chok Ho ,  Teruo Sasagawa ,  Xiaoming Yan ,  Todd Lyle Zion

IPC分类号： B44C1/22 ,  C23F1/08

CPC分类号： H01L21/32135 ,  B01D53/002 ,  B01D2257/11 ,  B01D2257/2027 ,  H01L21/31116

摘要： The efficiency of an etching process may be increased in various ways, and the cost of an etching process may be decreased. Unused etchant may be isolated and recirculated during the etching process. Etching byproducts may be collected and removed from the etching system during the etching process. Components of the etchant may be isolated and used to general additional etchant. Either or both of the etchant or the layers being etched may also be optimized for a particular etching process.

摘要翻译： 可以以各种方式增加蚀刻工艺的效率，并且可以降低蚀刻工艺的成本。 未蚀刻的蚀刻剂可以在蚀刻过程中被隔离并再循环。 蚀刻副产物可以在蚀刻过程中从蚀刻系统中收集和去除。 蚀刻剂的组分可以被分离并用于一般的另外的蚀刻剂。 蚀刻剂或被蚀刻的层中的任一个或两者也可以针对特定的蚀刻工艺进行优化。

公开(公告)号：US20080102650A1

公开(公告)日：2008-05-01

申请号：US11554097

申请日：2006-10-30

申请人： Edward Dennis Adams ,  Jay Sanford Burnham ,  Evgeni Gousev ,  James Spiros Nakos ,  Heather Elizabeth Preuss ,  Joseph Francis Shepard

发明人： Edward Dennis Adams ,  Jay Sanford Burnham ,  Evgeni Gousev ,  James Spiros Nakos ,  Heather Elizabeth Preuss ,  Joseph Francis Shepard

IPC分类号： H01L21/31

CPC分类号： H01L21/02332 ,  H01L21/0214 ,  H01L21/02337 ,  H01L21/28202 ,  H01L21/3144

摘要： A method of forming a nitrided silicon oxide layer. The method includes: forming a silicon dioxide layer on a surface of a silicon substrate; performing a rapid thermal nitridation of the silicon dioxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form an initial nitrided silicon oxide layer; and performing a rapid thermal oxidation or anneal of the initial nitrided silicon oxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form a nitrided silicon oxide layer. Also a method of forming a MOSFET with a nitrided silicon oxide dielectric layer.

摘要翻译： 形成氮化硅氧化物层的方法。 该方法包括：在硅衬底的表面上形成二氧化硅层; 在小于或等于约900℃的温度和大于约500托的压力下进行二氧化硅层的快速热氮化，以形成初始氮化氧化硅层; 并且在小于或等于约900℃的温度和大于约500托的压力下进行初始氮化硅氧化物层的快速热氧化或退火以形成氮化的氧化硅层。 还有一种形成具有氮化硅氧化物介电层的MOSFET的方法。

公开(公告)号：US20060275977A1

公开(公告)日：2006-12-07

申请号：US11500254

申请日：2006-08-07

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.