公开(公告)号：US20120274647A1

公开(公告)日：2012-11-01

申请号：US13094687

申请日：2011-04-26

申请人： Je-Hsiung Lan ,  Sang-June Park ,  Jonghae Kim ,  Evgeni Gousev ,  Matthew Nowak ,  Philip J. Stephanou ,  Justin Black ,  Kurt Petersen ,  Srinivasan Ganapathi

发明人： Je-Hsiung Lan ,  Sang-June Park ,  Jonghae Kim ,  Evgeni Gousev ,  Matthew Nowak ,  Philip J. Stephanou ,  Justin Black ,  Kurt Petersen ,  Srinivasan Ganapathi

IPC分类号： H01L41/053 ,  G09G5/39 ,  H01L41/22 ,  G06T1/60

CPC分类号： H03H3/0072 ,  H03H9/2447 ,  Y10T29/42

摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a sacrificial layer is deposited on an insulating substrate. A lower electrode layer is formed proximate the sacrificial layer. A piezoelectric layer is deposited on the lower electrode layer. An upper electrode layer is formed on the piezoelectric layer. At least a portion of the sacrificial layer is removed to define a cavity such that at least a portion of the lower electrode layer is spaced apart from the insulating substrate.

摘要翻译： 本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。 在一个方面，牺牲层沉积在绝缘衬底上。 在牺牲层附近形成下电极层。 压电层沉积在下电极层上。 在压电层上形成上电极层。 去除牺牲层的至少一部分以限定空腔，使得下电极层的至少一部分与绝缘基板间隔开。

公开(公告)号：US20120293520A1

公开(公告)日：2012-11-22

申请号：US13111683

申请日：2011-05-19

申请人： Changhan Yun ,  Sang-June Park ,  Chi Shun Lo ,  Jonghae Kim ,  Je-Hsiung Lan ,  Sanghoon Joo

发明人： Changhan Yun ,  Sang-June Park ,  Chi Shun Lo ,  Jonghae Kim ,  Je-Hsiung Lan ,  Sanghoon Joo

IPC分类号： G06T1/00 ,  H03H9/17

CPC分类号： H03H9/173 ,  H03H9/02228

摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, resonator apparatus includes a first conductive layer including a first electrode and a second electrode. The first electrode is coupled to receive a first input signal, and the second electrode is coupled to provide a first output signal. A piezoelectric layer includes a piezoelectric material. The piezoelectric layer has a first side and a second side opposite the first side. The first side is proximate the first conductive layer, and the second side is electrically isolated from ground. In some examples, the second side of the piezoelectric layer can be exposed and/or electrically de-coupled from one or more components.

摘要翻译： 本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。 在一个方面，谐振器装置包括包括第一电极和第二电极的第一导电层。 第一电极被耦合以接收第一输入信号，并且第二电极被耦合以提供第一输出信号。 压电层包括压电材料。 压电层具有与第一侧相对的第一侧和第二侧。 第一侧靠近第一导电层，第二侧与地电隔离。 在一些示例中，压电层的第二面可以暴露和/或从一个或多个部件电脱耦合。

公开(公告)号：US20120286886A1

公开(公告)日：2012-11-15

申请号：US13107764

申请日：2011-05-13

申请人： Jonghae Kim ,  Je-Hsiung Lan ,  Changhan Yun ,  Chi Shun Lo ,  Matthew Nowak

发明人： Jonghae Kim ,  Je-Hsiung Lan ,  Changhan Yun ,  Chi Shun Lo ,  Matthew Nowak

IPC分类号： H03B7/14

CPC分类号： H03H9/2426 ,  H03H9/02228 ,  H03H9/2405 ,  H03H9/462 ,  H03H2009/241

摘要： Electromechanical systems resonator structures, devices, circuits, and systems are disclosed. In one aspect, an oscillator includes an active component and a passive component connected in a feedback configuration. The passive component includes one or more contour mode resonators (CMR). A CMR includes a piezoelectric layer disposed between a first conductive layer and a second conductive layer. The conductive layers include an input electrode and an output electrode. The passive component is configured to output a first resonant frequency and a second resonant frequency, which is an odd integer harmonic of the first resonant frequency. The active component is configured to output a signal including the first resonant frequency and the second resonant frequency. This output signal can be a substantially square wave signal, which can serve as a clock in various applications.

摘要翻译： 公开了机电系统谐振器结构，器件，电路和系统。 一方面，振荡器包括以反馈配置连接的有源部件和无源部件。 无源部件包括一个或多个轮廓模式谐振器（CMR）。 CMR包括设置在第一导电层和第二导电层之间的压电层。 导电层包括输入电极和输出电极。 无源部件被配置为输出第一谐振频率和第二谐振频率，其是第一谐振频率的奇整数谐波。 有源部件被配置为输出包括第一谐振频率和第二谐振频率的信号。 该输出信号可以是基本上为方波信号，其可以用作各种应用中的时钟。

公开(公告)号：US08471643B2

公开(公告)日：2013-06-25

申请号：US13107764

申请日：2011-05-13

申请人： Jonghae Kim ,  Je-Hsiung Lan ,  Changhan Yun ,  Chi Shun Lo ,  Matthew Nowak

发明人： Jonghae Kim ,  Je-Hsiung Lan ,  Changhan Yun ,  Chi Shun Lo ,  Matthew Nowak

IPC分类号： H03B5/30

CPC分类号： H03H9/2426 ,  H03H9/02228 ,  H03H9/2405 ,  H03H9/462 ,  H03H2009/241

摘要： Electromechanical systems resonator structures, devices, circuits, and systems are disclosed. In one aspect, an oscillator includes an active component and a passive component connected in a feedback configuration. The passive component includes one or more contour mode resonators (CMR). A CMR includes a piezoelectric layer disposed between a first conductive layer and a second conductive layer. The conductive layers include an input electrode and an output electrode. The passive component is configured to output a first resonant frequency and a second resonant frequency, which is an odd integer harmonic of the first resonant frequency. The active component is configured to output a signal including the first resonant frequency and the second resonant frequency. This output signal can be a substantially square wave signal, which can serve as a clock in various applications.

摘要翻译： 公开了机电系统谐振器结构，器件，电路和系统。 一方面，振荡器包括以反馈配置连接的有源部件和无源部件。 无源部件包括一个或多个轮廓模式谐振器（CMR）。 CMR包括设置在第一导电层和第二导电层之间的压电层。 导电层包括输入电极和输出电极。 无源部件被配置为输出第一谐振频率和第二谐振频率，其是第一谐振频率的奇整数谐波。 有源部件被配置为输出包括第一谐振频率和第二谐振频率的信号。 该输出信号可以是基本上为方波信号，其可以用作各种应用中的时钟。

公开(公告)号：US20120199949A1

公开(公告)日：2012-08-09

申请号：US13021151

申请日：2011-02-04

申请人： Je-Hsiung Lan ,  Matthew Michael Nowak ,  Evgeni P. Gousev ,  Jonghae Kim ,  Clarence Chui

发明人： Je-Hsiung Lan ,  Matthew Michael Nowak ,  Evgeni P. Gousev ,  Jonghae Kim ,  Clarence Chui

IPC分类号： H01L29/92 ,  H01L21/62

CPC分类号： H01L28/82 ,  H01G4/012 ,  H01G4/10 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/87 ,  H01L29/945 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311

摘要： Higher capacitance density is achieved by increasing a surface area of a capacitor. A larger surface area may be obtained by forming isotropic ball shapes (a concave surface) in the trenches on the semiconductor die. The concave surfaces are fabricated by depositing bilayers of amorphous-silicon and silicon oxide. Openings are patterned in the silicon oxide hard mask for trenches. The openings are transferred to the amorphous-silicon layers through isotropic etching to form concave surfaces. Conducting, insulating, and conducting layers are deposited on the concave surfaces of the trenches by atomic layer deposition.

摘要翻译： 通过增加电容器的表面积来实现更高的电容密度。 可以通过在半导体管芯上的沟槽中形成各向同性球形（凹面）来获得更大的表面积。 通过沉积非晶硅和氧化硅的双层来制造凹面。 在用于沟槽的氧化硅硬掩模中图案化开口。 通过各向同性蚀刻将开口转移到非晶硅层以形成凹面。 导电，绝缘和导电层通过原子层沉积沉积在沟槽的凹面上。

公开(公告)号：US08093982B2

公开(公告)日：2012-01-10

申请号：US12731393

申请日：2010-03-25

申请人： Jonghae Kim ,  Milind P. Shah ,  Chi Shun Lo ,  Je-Hsiung Lan ,  Xia Li ,  Matthew Michael Nowak

发明人： Jonghae Kim ,  Milind P. Shah ,  Chi Shun Lo ,  Je-Hsiung Lan ,  Xia Li ,  Matthew Michael Nowak

IPC分类号： H01F5/00

CPC分类号： H01L28/10 ,  H01F2017/004 ,  H01L21/84 ,  H01L23/645 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inductor or transformer for use in integrated circuit devices that includes a high-resistivity substrate. The inductor includes a plurality of conductive traces around the substrate forming a continuous conductive path from a first to a second port. The conductive path can be solenoid-shaped. Some of the conductive traces can be formed during back-end-of-line processing or backside plating of an integrated circuit die. The transformer includes a first inductor with input and output ports, and a first continuous conductive path therebetween; and a second inductor with input and output ports, and a second continuous conductive path therebetween. The second inductor is independent of and electromagnetically coupled to the first inductor. The first and second conductive paths can be solenoid-shaped. The first conductive path can be interleaved with the second conductive path.

摘要翻译： 一种用于集成电路器件的电感器或变压器，其包括高电阻率衬底。 电感器包括围绕衬底的多个导电迹线，形成从第一端口到第二端口的连续导电路径。 导电路径可以是螺线管形的。 一些导电迹线可以在集成电路管芯的后端处理或背面电镀期间形成。 变压器包括具有输入和输出端口的第一电感器和它们之间的第一连续导电路径; 以及具有输入和输出端口的第二电感器以及它们之间的第二连续导电路径。 第二电感器与第一电感器无关并与其电磁耦合。 第一和第二导电路径可以是螺线管形的。 第一导电路径可以与第二导电路径交错。

公开(公告)号：US08492874B2

公开(公告)日：2013-07-23

申请号：US13021151

申请日：2011-02-04

申请人： Je-Hsiung Lan ,  Matthew Michael Nowak ,  Evgeni P. Gousev ,  Jonghae Kim ,  Clarence Chui

发明人： Je-Hsiung Lan ,  Matthew Michael Nowak ,  Evgeni P. Gousev ,  Jonghae Kim ,  Clarence Chui

IPC分类号： H01G4/10 ,  H01G4/12 ,  H01L23/5222 ,  H01L28/82 ,  H01L29/945 ,  H01L23/642

CPC分类号： H01L28/82 ,  H01G4/012 ,  H01G4/10 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/87 ,  H01L29/945 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311

摘要： Higher capacitance density is achieved by increasing a surface area of a capacitor. A larger surface area may be obtained by forming isotropic ball shapes (a concave surface) in the trenches on the semiconductor die. The concave surfaces are fabricated by depositing bilayers of amorphous-silicon and silicon oxide. Openings are patterned in the silicon oxide hard mask for trenches. The openings are transferred to the amorphous-silicon layers through isotropic etching to form concave surfaces. Conducting, insulating, and conducting layers are deposited on the concave surfaces of the trenches by atomic layer deposition.

摘要翻译： 通过增加电容器的表面积来实现更高的电容密度。 可以通过在半导体管芯上的沟槽中形成各向同性球形（凹面）来获得更大的表面积。 通过沉积非晶硅和氧化硅的双层来制造凹面。 在用于沟槽的氧化硅硬掩模中图案化开口。 通过各向同性蚀刻将开口转移到非晶硅层以形成凹面。 导电，绝缘和导电层通过原子层沉积沉积在沟槽的凹面上。

公开(公告)号：US20110234357A1

公开(公告)日：2011-09-29

申请号：US12731393

申请日：2010-03-25

申请人： Jonghae Kim ,  Milind P. Shah ,  Chi Shun Lo ,  Je-Hsiung Lan ,  Xia Li ,  Matthew Michael Nowak

发明人： Jonghae Kim ,  Milind P. Shah ,  Chi Shun Lo ,  Je-Hsiung Lan ,  Xia Li ,  Matthew Michael Nowak

IPC分类号： H01F5/00

CPC分类号： H01L28/10 ,  H01F2017/004 ,  H01L21/84 ,  H01L23/645 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inductor or transformer for use in integrated circuit devices that includes a high-resistivity substrate. The inductor includes a plurality of conductive traces around the substrate forming a continuous conductive path from a first to a second port. The conductive path can be solenoid-shaped. Some of the conductive traces can be formed during back-end-of-line processing or backside plating of an integrated circuit die. The transformer includes a first inductor with input and output ports, and a first continuous conductive path therebetween; and a second inductor with input and output ports, and a second continuous conductive path therebetween. The second inductor is independent of and electromagnetically coupled to the first inductor. The first and second conductive paths can be solenoid-shaped. The first conductive path can be interleaved with the second conductive path.

摘要翻译： 一种用于集成电路器件的电感器或变压器，其包括高电阻率衬底。 电感器包括围绕衬底的多个导电迹线，形成从第一端口到第二端口的连续导电路径。 导电路径可以是螺线管形的。 一些导电迹线可以在集成电路管芯的后端处理或背面电镀期间形成。 变压器包括具有输入和输出端口的第一电感器和它们之间的第一连续导电路径; 以及具有输入和输出端口的第二电感器以及它们之间的第二连续导电路径。 第二电感器与第一电感器无关并与其电磁耦合。 第一和第二导电路径可以是螺线管形的。 第一导电路径可以与第二导电路径交错。

公开(公告)号：US20130120951A1

公开(公告)日：2013-05-16

申请号：US13356717

申请日：2012-01-24

申请人： Chengjie Zuo ,  Changhan Yun ,  Sang-June Park ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Sang-June Park ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

IPC分类号： H05K1/03 ,  H01L21/60 ,  H05K7/06 ,  H01L21/58

CPC分类号： H01L27/0688 ,  H01L2224/18

摘要： A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.

摘要翻译： 芯片组包括玻璃板，石英或蓝宝石片，以及在第一基底层的第一面上具有至少一个第一电路层的第一晶片。 第一晶片连接到片材，使得至少一个第一电路层位于第一基片层和片之间。 具有在第二衬底层的第一侧上的至少一个第二电路层的第二晶片连接到第一衬底层，使得至少一个第二电路层位于第二衬底层和第一衬底层之间。 还有一种形成芯片组的方法。

公开(公告)号：US20140035702A1

公开(公告)日：2014-02-06

申请号：US13563252

申请日：2012-07-31

申请人： Justin Phelps Black ,  Philip Jason Stephanou ,  Jonghae Kim ,  Je-Hsiung Jeffrey Lan ,  Sang-June Park ,  Changhan Hobie Yun ,  Chi Shun Lo ,  Chengjie Zuo

发明人： Justin Phelps Black ,  Philip Jason Stephanou ,  Jonghae Kim ,  Je-Hsiung Jeffrey Lan ,  Sang-June Park ,  Changhan Hobie Yun ,  Chi Shun Lo ,  Chengjie Zuo

IPC分类号： H03H9/00 ,  H03H7/01

CPC分类号： H03H7/075 ,  H03H9/465 ,  H03H2007/006

摘要： This disclosure provides implementations of filters and filter topologies, circuits, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes one or more LC resonant circuit stages. In some implementations, each LC stage includes an inductor and a capacitor. Each LC stage also has a corresponding resonant frequency. The one or more LC stages are arranged to produce an unmodified passband over a range of frequencies having a corresponding bandwidth. One or more microelectromechanical systems (MEMS) resonators are arranged with the one or more LC stages. The one or more MEMS resonators are arranged with the one or more LC stages so as to modify characteristics of the unmodified passband such that the hybrid filter produces a modified passband having a modified bandwidth and one or more other modified band characteristics.

摘要翻译： 本公开提供了滤波器和滤波器拓扑，电路，结构，设备，装置，系统和相关过程的实现。 在一个方面，器件包括一个或多个LC谐振电路级。 在一些实现中，每个LC级包括电感器和电容器。 每个LC级还具有相应的谐振频率。 一个或多个LC级布置成在具有相应带宽的频率范围上产生未修改的通带。 一个或多个微机电系统（MEMS）谐振器与一个或多个LC级布置。 一个或多个MEMS谐振器被布置成具有一个或多个LC级，以便修改未修改的通带的特性，使得混合滤波器产生具有修改的带宽和一个或多个其它修改的频带特性的修改的通带。